{"id":"https://openalex.org/W3006667757","doi":"https://doi.org/10.1109/tvlsi.2020.2968904","title":"Design Space Exploration for Chiplet-Assembly-Based Processors","display_name":"Design Space Exploration for Chiplet-Assembly-Based Processors","publication_year":2020,"publication_date":"2020-02-13","ids":{"openalex":"https://openalex.org/W3006667757","doi":"https://doi.org/10.1109/tvlsi.2020.2968904","mag":"3006667757"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2020.2968904","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2020.2968904","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5036103216","display_name":"Saptadeep Pal","orcid":"https://orcid.org/0000-0002-8777-8573"},"institutions":[{"id":"https://openalex.org/I161318765","display_name":"University of California, Los Angeles","ror":"https://ror.org/046rm7j60","country_code":"US","type":"education","lineage":["https://openalex.org/I161318765"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Saptadeep Pal","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of California at Los Angeles, Los Angeles, USA"],"raw_orcid":"https://orcid.org/0000-0002-8777-8573","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of California at Los Angeles, Los Angeles, USA","institution_ids":["https://openalex.org/I161318765"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5079148770","display_name":"Daniel Petrisko","orcid":"https://orcid.org/0000-0002-0555-6919"},"institutions":[{"id":"https://openalex.org/I157725225","display_name":"University of Illinois Urbana-Champaign","ror":"https://ror.org/047426m28","country_code":"US","type":"education","lineage":["https://openalex.org/I157725225"]},{"id":"https://openalex.org/I201448701","display_name":"University of Washington","ror":"https://ror.org/00cvxb145","country_code":"US","type":"education","lineage":["https://openalex.org/I201448701"]},{"id":"https://openalex.org/I58610484","display_name":"Seattle University","ror":"https://ror.org/02jqc0m91","country_code":"US","type":"education","lineage":["https://openalex.org/I58610484"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Daniel Petrisko","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Illinois at Urbana\u2013Champaign, Champaign, USA","University of Washington, Seattle, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Illinois at Urbana\u2013Champaign, Champaign, USA","institution_ids":["https://openalex.org/I157725225"]},{"raw_affiliation_string":"University of Washington, Seattle, USA","institution_ids":["https://openalex.org/I201448701","https://openalex.org/I58610484"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5067547869","display_name":"Rakesh Kumar","orcid":"https://orcid.org/0000-0002-3290-2629"},"institutions":[{"id":"https://openalex.org/I157725225","display_name":"University of Illinois Urbana-Champaign","ror":"https://ror.org/047426m28","country_code":"US","type":"education","lineage":["https://openalex.org/I157725225"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Rakesh Kumar","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Illinois at Urbana\u2013Champaign, Champaign, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Illinois at Urbana\u2013Champaign, Champaign, USA","institution_ids":["https://openalex.org/I157725225"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5084229134","display_name":"Puneet Gupta","orcid":"https://orcid.org/0000-0002-6188-1134"},"institutions":[{"id":"https://openalex.org/I161318765","display_name":"University of California, Los Angeles","ror":"https://ror.org/046rm7j60","country_code":"US","type":"education","lineage":["https://openalex.org/I161318765"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Puneet Gupta","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of California at Los Angeles, Los Angeles, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of California at Los Angeles, Los Angeles, USA","institution_ids":["https://openalex.org/I161318765"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":3.6391,"has_fulltext":false,"cited_by_count":38,"citation_normalized_percentile":{"value":0.93370737,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":100},"biblio":{"volume":"28","issue":"4","first_page":"1062","last_page":"1073"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.7071719169616699},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6627308130264282},{"id":"https://openalex.org/keywords/turnaround-time","display_name":"Turnaround time","score":0.6309969425201416},{"id":"https://openalex.org/keywords/personalization","display_name":"Personalization","score":0.5995911359786987},{"id":"https://openalex.org/keywords/space-exploration","display_name":"Space exploration","score":0.4661966860294342},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.46094071865081787},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4574197828769684},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4547107517719269},{"id":"https://openalex.org/keywords/systems-engineering","display_name":"Systems engineering","score":0.4245019257068634},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.33462977409362793},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2199280858039856},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.10943073034286499}],"concepts":[{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.7071719169616699},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6627308130264282},{"id":"https://openalex.org/C176553487","wikidata":"https://www.wikidata.org/wiki/Q7855819","display_name":"Turnaround time","level":2,"score":0.6309969425201416},{"id":"https://openalex.org/C183003079","wikidata":"https://www.wikidata.org/wiki/Q1000371","display_name":"Personalization","level":2,"score":0.5995911359786987},{"id":"https://openalex.org/C104060986","wikidata":"https://www.wikidata.org/wiki/Q180046","display_name":"Space exploration","level":2,"score":0.4661966860294342},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.46094071865081787},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4574197828769684},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4547107517719269},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.4245019257068634},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.33462977409362793},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2199280858039856},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.10943073034286499},{"id":"https://openalex.org/C136764020","wikidata":"https://www.wikidata.org/wiki/Q466","display_name":"World Wide Web","level":1,"score":0.0},{"id":"https://openalex.org/C146978453","wikidata":"https://www.wikidata.org/wiki/Q3798668","display_name":"Aerospace engineering","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2020.2968904","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2020.2968904","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.7099999785423279,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[{"id":"https://openalex.org/G269703682","display_name":"Heterogeneously Integrated Memory Subsystem for the IoT Era","funder_award_id":"MRP-17-454999","funder_id":"https://openalex.org/F4320333677","funder_display_name":"Office of the President, University of California"},{"id":"https://openalex.org/G3108613685","display_name":null,"funder_award_id":"N00014-16-1-263","funder_id":"https://openalex.org/F4320332180","funder_display_name":"Defense Advanced Research Projects Agency"}],"funders":[{"id":"https://openalex.org/F4320332180","display_name":"Defense Advanced Research Projects Agency","ror":"https://ror.org/02caytj08"},{"id":"https://openalex.org/F4320333677","display_name":"Office of the President, University of California","ror":null}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":41,"referenced_works":["https://openalex.org/W1533120213","https://openalex.org/W1815597787","https://openalex.org/W2010540152","https://openalex.org/W2011734692","https://openalex.org/W2034062945","https://openalex.org/W2036216970","https://openalex.org/W2046074651","https://openalex.org/W2071568619","https://openalex.org/W2099708455","https://openalex.org/W2103670614","https://openalex.org/W2112121929","https://openalex.org/W2112764807","https://openalex.org/W2118507980","https://openalex.org/W2120368896","https://openalex.org/W2124569501","https://openalex.org/W2145021036","https://openalex.org/W2145929661","https://openalex.org/W2163835931","https://openalex.org/W2170382128","https://openalex.org/W2170863844","https://openalex.org/W2234584938","https://openalex.org/W2299026636","https://openalex.org/W2335541622","https://openalex.org/W2515277349","https://openalex.org/W2518432791","https://openalex.org/W2532719504","https://openalex.org/W2549081672","https://openalex.org/W2593535610","https://openalex.org/W2745282586","https://openalex.org/W2749199255","https://openalex.org/W2906926620","https://openalex.org/W4205236169","https://openalex.org/W4235580647","https://openalex.org/W4238549726","https://openalex.org/W4240540736","https://openalex.org/W6631882261","https://openalex.org/W6678793989","https://openalex.org/W6684912905","https://openalex.org/W6697834529","https://openalex.org/W6703148540","https://openalex.org/W6758076146"],"related_works":["https://openalex.org/W2108386578","https://openalex.org/W2020034302","https://openalex.org/W2099965745","https://openalex.org/W2146527276","https://openalex.org/W2754086592","https://openalex.org/W3147787617","https://openalex.org/W1994609733","https://openalex.org/W1973113362","https://openalex.org/W1485852435","https://openalex.org/W2144434960"],"abstract_inverted_index":{"Recent":[0],"advancements":[1],"in":[2,115,133,142],"2.5-D":[3],"integration":[4],"technologies":[5],"have":[6],"made":[7],"chiplet":[8,51,67,85,126],"assembly":[9,16,86,127],"a":[10,20,49,119],"viable":[11],"system":[12],"design":[13,25,29,62,81],"approach.":[14],"Chiplet":[15],"is":[17],"emerging":[18],"as":[19],"new":[21],"paradigm":[22],"for":[23,66],"heterogeneous":[24,88],"at":[26],"lower":[27],"cost,":[28],"effort,":[30],"and":[31,34,82,90,123,148],"turnaround":[32],"time":[33],"enables":[35,71],"low-cost":[36],"customization":[37,93],"of":[38,43,78,99,125,135,151],"hardware.":[39],"However,":[40],"the":[41,59,75,97,146],"success":[42],"this":[44],"approach":[45],"depends":[46],"on":[47],"identifying":[48],"minimum":[50,76],"set":[52,77],"which":[53,70],"delivers":[54],"these":[55],"benefits.":[56],"We":[57],"develop":[58],"first":[60],"microarchitectural":[61],"space":[63],"exploration":[64],"framework":[65],"assembly-based":[68],"processors":[69],"us":[72],"to":[73,80,107,112,139],"identify":[74],"chiplets":[79,106],"manufacture.":[83],"Since":[84],"makes":[87],"technology":[89],"cost-effective":[91],"application-dependent":[92],"possible,":[94],"we":[95],"show":[96],"benefits":[98],"using":[100],"multiple":[101,105],"systems":[102],"built":[103],"from":[104],"service":[108],"diverse":[109],"workloads":[110],"(up":[111,138],"35%":[113],"improvement":[114,141],"energy-delay":[116],"product":[117],"over":[118,129],"single":[120],"best":[121],"system)":[122],"advantages":[124],"approaches":[128],"system-on-chip":[130],"(SoC)":[131],"methodology":[132],"terms":[134],"total":[136],"cost":[137],"72%":[140],"cost)":[143],"while":[144],"satisfying":[145],"energy":[147],"performance":[149],"constraints":[150],"individual":[152],"applications.":[153]},"counts_by_year":[{"year":2026,"cited_by_count":6},{"year":2025,"cited_by_count":11},{"year":2024,"cited_by_count":5},{"year":2023,"cited_by_count":5},{"year":2022,"cited_by_count":6},{"year":2021,"cited_by_count":4},{"year":2020,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}