{"id":"https://openalex.org/W3000168951","doi":"https://doi.org/10.1109/tvlsi.2019.2962501","title":"Optimizing FPGA Logic Circuitry for Variable Voltage Supplies","display_name":"Optimizing FPGA Logic Circuitry for Variable Voltage Supplies","publication_year":2020,"publication_date":"2020-01-14","ids":{"openalex":"https://openalex.org/W3000168951","doi":"https://doi.org/10.1109/tvlsi.2019.2962501","mag":"3000168951"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2019.2962501","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2019.2962501","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100743340","display_name":"Ibrahim Ahmed","orcid":"https://orcid.org/0000-0003-2696-3086"},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Ibrahim Ahmed","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Toronto, Toronto, Canada"],"raw_orcid":"https://orcid.org/0000-0003-2696-3086","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Toronto, Toronto, Canada","institution_ids":["https://openalex.org/I185261750"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5053953264","display_name":"Linda L. Shen","orcid":null},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Linda L. Shen","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Toronto, Toronto, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Toronto, Toronto, Canada","institution_ids":["https://openalex.org/I185261750"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5030184404","display_name":"Vaughn Betz","orcid":"https://orcid.org/0000-0003-0528-6493"},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Vaughn Betz","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Toronto, Toronto, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Toronto, Toronto, Canada","institution_ids":["https://openalex.org/I185261750"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5100743340"],"corresponding_institution_ids":["https://openalex.org/I185261750"],"apc_list":null,"apc_paid":null,"fwci":0.9363,"has_fulltext":false,"cited_by_count":17,"citation_normalized_percentile":{"value":0.73967707,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":"28","issue":"4","first_page":"890","last_page":"903"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.8516412973403931},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7825410962104797},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5942394733428955},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.5543053150177002},{"id":"https://openalex.org/keywords/voltage-reduction","display_name":"Voltage reduction","score":0.5388100147247314},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.47983166575431824},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4673037528991699},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4469708502292633},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3962520360946655},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3479903042316437},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.24648746848106384},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.22310221195220947},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.10366323590278625}],"concepts":[{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.8516412973403931},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7825410962104797},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5942394733428955},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.5543053150177002},{"id":"https://openalex.org/C2780745134","wikidata":"https://www.wikidata.org/wiki/Q7940751","display_name":"Voltage reduction","level":3,"score":0.5388100147247314},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.47983166575431824},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4673037528991699},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4469708502292633},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3962520360946655},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3479903042316437},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.24648746848106384},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.22310221195220947},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.10366323590278625},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2019.2962501","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2019.2962501","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8399999737739563,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":47,"referenced_works":["https://openalex.org/W1518236483","https://openalex.org/W1523051745","https://openalex.org/W1967128905","https://openalex.org/W1977850862","https://openalex.org/W1989227777","https://openalex.org/W2005671831","https://openalex.org/W2022202043","https://openalex.org/W2030765577","https://openalex.org/W2034919323","https://openalex.org/W2041053190","https://openalex.org/W2045704975","https://openalex.org/W2064907250","https://openalex.org/W2074599790","https://openalex.org/W2085583524","https://openalex.org/W2095258817","https://openalex.org/W2105281355","https://openalex.org/W2107419853","https://openalex.org/W2113645429","https://openalex.org/W2116094656","https://openalex.org/W2116750875","https://openalex.org/W2126810113","https://openalex.org/W2129267471","https://openalex.org/W2133156997","https://openalex.org/W2137769675","https://openalex.org/W2138383740","https://openalex.org/W2142002524","https://openalex.org/W2153552399","https://openalex.org/W2158101706","https://openalex.org/W2166029537","https://openalex.org/W2168843308","https://openalex.org/W2264331490","https://openalex.org/W2295327519","https://openalex.org/W2397888180","https://openalex.org/W2525415380","https://openalex.org/W2542189141","https://openalex.org/W2555473955","https://openalex.org/W2610319614","https://openalex.org/W2798956872","https://openalex.org/W2904347961","https://openalex.org/W2911751195","https://openalex.org/W2987526256","https://openalex.org/W3152435103","https://openalex.org/W4239385313","https://openalex.org/W4250986744","https://openalex.org/W4256629673","https://openalex.org/W6679301951","https://openalex.org/W6682380216"],"related_works":["https://openalex.org/W2074063066","https://openalex.org/W2003435315","https://openalex.org/W2141752451","https://openalex.org/W2107701025","https://openalex.org/W2065489212","https://openalex.org/W2145701142","https://openalex.org/W3145722221","https://openalex.org/W2384487777","https://openalex.org/W2088630761","https://openalex.org/W2074301316"],"abstract_inverted_index":{"Unlike":[0],"central":[1],"processing":[2],"units":[3],"(CPUs),":[4],"field-programmable":[5],"gate":[6,80],"arrays":[7],"(FPGAs)":[8],"have":[9,22,152],"conventionally":[10],"been":[11],"powered":[12],"with":[13,67],"a":[14,123,178],"fixed":[15],"supply":[16,48],"voltage":[17,27,49,95],"(Vdd).":[18],"However,":[19],"recent":[20],"efforts":[21],"shown":[23],"that":[24,53,165],"adopting":[25],"dynamic":[26],"scaling":[28],"reduces":[29,110],"FPGA":[30,44,99,116,146,176],"power":[31],"consumption":[32],"significantly.":[33],"In":[34],"this":[35],"article,":[36],"we":[37,73],"analyze":[38],"the":[39,82,85,90,98,111,115,167,183,187],"delay":[40,69,154],"sensitivity":[41,70,155],"of":[42,89,114,133,166],"different":[43],"circuit":[45],"elements":[46],"to":[47,71,122,156],"changes":[50],"and":[51,92,101,128,139,151,172],"determine":[52],"conventional":[54,124,184],"lookup":[55],"table":[56],"(LUT)":[57],"designs":[58,148],"greatly":[59],"impact":[60],"variable":[61],"Vdd":[62,131,171],"operation.":[63],"To":[64],"build":[65],"FPGAs":[66],"lower":[68,153],"Vdd,":[72],"propose":[74],"several":[75],"new":[76],"LUT":[77],"designs,":[78],"including":[79],"boosting":[81],"LUT,":[83,91],"decoding":[84],"slowest":[86],"two":[87],"inputs":[88],"using":[93],"separate":[94],"islands":[96],"for":[97],"LUTs":[100],"routing.":[102],"Our":[103,174],"fastest":[104],"proposed":[105,145],"design":[106,125,185],"(decode":[107],"driver":[108],"island)":[109],"area-delay":[112],"product":[113,162],"logic":[117],"plus":[118],"routing":[119],"tile":[120,147],"compared":[121],"by":[126],"12%":[127],"52%":[129],"at":[130,169,186],"values":[132],"0.8":[134],"V":[135],"(the":[136],"nominal":[137,170],"voltage)":[138],"0.6":[140],"V,":[141],"respectively.":[142],"Since":[143],"our":[144],"are":[149],"faster":[150],"voltage,":[157],"they":[158],"offer":[159],"better":[160],"Energy-Delay2":[161],"(ED2)":[163],"than":[164],"baseline":[168],"below.":[173],"decode-driver-island":[175],"achieves":[177],"26%":[179],"ED2":[180,190],"reduction":[181],"over":[182],"most":[188],"efficient":[189],"operating":[191],"point.":[192]},"counts_by_year":[{"year":2026,"cited_by_count":2},{"year":2025,"cited_by_count":4},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":5},{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}