{"id":"https://openalex.org/W2999951849","doi":"https://doi.org/10.1109/tvlsi.2019.2958989","title":"A Methodology to Capture Fine-Grained Internal Visibility During Multisession Silicon Debug","display_name":"A Methodology to Capture Fine-Grained Internal Visibility During Multisession Silicon Debug","publication_year":2020,"publication_date":"2020-01-07","ids":{"openalex":"https://openalex.org/W2999951849","doi":"https://doi.org/10.1109/tvlsi.2019.2958989","mag":"2999951849"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2019.2958989","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2019.2958989","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100712184","display_name":"Binod Kumar","orcid":"https://orcid.org/0000-0002-0479-9855"},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Binod Kumar","raw_affiliation_strings":["Department of Electrical Engineering, Computer Architecture and Dependable Systems Laboratory (CADSL), IIT Bombay, Mumbai, India"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Computer Architecture and Dependable Systems Laboratory (CADSL), IIT Bombay, Mumbai, India","institution_ids":["https://openalex.org/I162827531"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5056749623","display_name":"Jay Adhaduk","orcid":"https://orcid.org/0000-0003-1833-5338"},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Jay Adhaduk","raw_affiliation_strings":["Department of Electrical Engineering, Computer Architecture and Dependable Systems Laboratory (CADSL), IIT Bombay, Mumbai, India"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Computer Architecture and Dependable Systems Laboratory (CADSL), IIT Bombay, Mumbai, India","institution_ids":["https://openalex.org/I162827531"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5066320524","display_name":"Kanad Basu","orcid":"https://orcid.org/0000-0002-6431-7512"},"institutions":[{"id":"https://openalex.org/I162577319","display_name":"The University of Texas at Dallas","ror":"https://ror.org/049emcs32","country_code":"US","type":"education","lineage":["https://openalex.org/I162577319"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kanad Basu","raw_affiliation_strings":["Department of Electrical and Computer Engineering, The University of Texas at Dallas, Richardson, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, The University of Texas at Dallas, Richardson, USA","institution_ids":["https://openalex.org/I162577319"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5027837299","display_name":"Masahiro Fujita","orcid":"https://orcid.org/0000-0002-6516-4175"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Masahiro Fujita","raw_affiliation_strings":["VLSI Design and Education Center (VDEC), The University of Tokyo, Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"VLSI Design and Education Center (VDEC), The University of Tokyo, Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5073587430","display_name":"Virendra Singh","orcid":"https://orcid.org/0000-0002-7035-7844"},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Virendra Singh","raw_affiliation_strings":["Department of Electrical Engineering, Computer Architecture and Dependable Systems Laboratory (CADSL), IIT Bombay, Mumbai, India"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Computer Architecture and Dependable Systems Laboratory (CADSL), IIT Bombay, Mumbai, India","institution_ids":["https://openalex.org/I162827531"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5100712184"],"corresponding_institution_ids":["https://openalex.org/I162827531"],"apc_list":null,"apc_paid":null,"fwci":0.5137,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.63174876,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"28","issue":"4","first_page":"1002","last_page":"1015"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/debugging","display_name":"Debugging","score":0.9424880743026733},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8398325443267822},{"id":"https://openalex.org/keywords/background-debug-mode-interface","display_name":"Background debug mode interface","score":0.7165594100952148},{"id":"https://openalex.org/keywords/session","display_name":"Session (web analytics)","score":0.5962623357772827},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5727909207344055},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5651599764823914},{"id":"https://openalex.org/keywords/visibility","display_name":"Visibility","score":0.5560500025749207},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5328711867332458},{"id":"https://openalex.org/keywords/real-time-computing","display_name":"Real-time computing","score":0.3624730110168457},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.35312098264694214},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.18391147255897522}],"concepts":[{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.9424880743026733},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8398325443267822},{"id":"https://openalex.org/C124774103","wikidata":"https://www.wikidata.org/wiki/Q4839640","display_name":"Background debug mode interface","level":3,"score":0.7165594100952148},{"id":"https://openalex.org/C2779182362","wikidata":"https://www.wikidata.org/wiki/Q17126187","display_name":"Session (web analytics)","level":2,"score":0.5962623357772827},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5727909207344055},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5651599764823914},{"id":"https://openalex.org/C123403432","wikidata":"https://www.wikidata.org/wiki/Q654068","display_name":"Visibility","level":2,"score":0.5560500025749207},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5328711867332458},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.3624730110168457},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.35312098264694214},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.18391147255897522},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C120665830","wikidata":"https://www.wikidata.org/wiki/Q14620","display_name":"Optics","level":1,"score":0.0},{"id":"https://openalex.org/C136764020","wikidata":"https://www.wikidata.org/wiki/Q466","display_name":"World Wide Web","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2019.2958989","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2019.2958989","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.6499999761581421,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":22,"referenced_works":["https://openalex.org/W1429120505","https://openalex.org/W1970455331","https://openalex.org/W1976197109","https://openalex.org/W2014071060","https://openalex.org/W2051695371","https://openalex.org/W2062677539","https://openalex.org/W2113717210","https://openalex.org/W2134518125","https://openalex.org/W2137410883","https://openalex.org/W2137769520","https://openalex.org/W2152406824","https://openalex.org/W2165139922","https://openalex.org/W2170454670","https://openalex.org/W2521100974","https://openalex.org/W2550447621","https://openalex.org/W2590124858","https://openalex.org/W2593952303","https://openalex.org/W2612262716","https://openalex.org/W2803640026","https://openalex.org/W2902445356","https://openalex.org/W6642685458","https://openalex.org/W6663557909"],"related_works":["https://openalex.org/W2354955167","https://openalex.org/W2162925013","https://openalex.org/W2351581202","https://openalex.org/W2978026406","https://openalex.org/W2388687068","https://openalex.org/W2366922255","https://openalex.org/W2000905221","https://openalex.org/W2399091034","https://openalex.org/W2390462575","https://openalex.org/W2358358756"],"abstract_inverted_index":{"Silicon":[0],"debugging":[1,28,43,65],"is":[2,25,52],"carried":[3],"out":[4],"in":[5,84,97,116,133,184,193],"multiple":[6],"sessions":[7],"which":[8,36],"are":[9,95],"characterized":[10],"by":[11],"run-and-halt":[12],"intervals.":[13],"One":[14],"of":[15,22,47,75,104,112,128,141,165],"the":[16,20,27,33,42,69,73,91,98,102,110,119,129,138,142,172,182,185,194],"important":[17,39],"criteria":[18],"for":[19,67,162],"success":[21],"this":[23],"method":[24],"that":[26,171],"infrastructure":[29],"should":[30],"capture":[31],"only":[32],"erroneous":[34,87],"data":[35,78,94,131],"can":[37,148,175],"add":[38],"insights":[40],"to":[41,151,190],"process.":[44],"However,":[45],"identification":[46],"such":[48],"suspect":[49],"clock":[50,88],"cycles":[51],"not":[53],"a":[54,64,113,134,152],"trivial":[55],"exercise":[56],"and":[57,90,181],"requires":[58],"an":[59],"systematic":[60],"approach.":[61],"We":[62,155],"propose":[63],"architecture":[66,121],"enhancing":[68],"multisession":[70],"procedure":[71],"using":[72],"technique":[74],"on-chip":[76,178],"debug":[77,93,130,144],"compression.":[79],"The":[80],"first":[81],"session":[82,100],"assists":[83],"identifying":[85],"those":[86],"cycles,":[89],"useful":[92],"collected":[96,143],"second":[99],"with":[101],"help":[103],"markers":[105],"called":[106],"tag":[107],"bits.":[108],"At":[109],"cost":[111],"minimal":[114],"increase":[115],"area":[117],"overhead,":[118],"proposed":[120,173],"achieves":[122],"finer":[123,153],"temporal":[124,186],"visibility":[125],"expansion":[126,183],"because":[127],"collection":[132],"segregated":[135],"manner.":[136],"During":[137],"offline":[139],"analysis":[140],"data,":[145],"error":[146,166],"localization":[147],"be":[149],"achieved":[150],"resolution.":[154],"evaluate":[156],"our":[157],"methodology":[158,174],"on":[159],"several":[160],"designs":[161],"different":[163],"kinds":[164],"configurations.":[167],"Experimental":[168],"results":[169],"show":[170],"achieve":[176],"better":[177],"storage":[179],"utilization":[180],"observation":[187],"window":[188],"compared":[189],"similar":[191],"techniques":[192],"literature.":[195]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":4}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
