{"id":"https://openalex.org/W2996590588","doi":"https://doi.org/10.1109/tvlsi.2019.2956100","title":"A Fast Settling Fractional-$N$ DPLL With Loop-Order Switching","display_name":"A Fast Settling Fractional-$N$ DPLL With Loop-Order Switching","publication_year":2019,"publication_date":"2019-12-19","ids":{"openalex":"https://openalex.org/W2996590588","doi":"https://doi.org/10.1109/tvlsi.2019.2956100","mag":"2996590588"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2019.2956100","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2019.2956100","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5042888819","display_name":"Pallavi Paliwal","orcid":"https://orcid.org/0000-0002-4821-5284"},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Pallavi Paliwal","raw_affiliation_strings":["IIT Bombay, Mumbai, India"],"raw_orcid":"https://orcid.org/0000-0002-4821-5284","affiliations":[{"raw_affiliation_string":"IIT Bombay, Mumbai, India","institution_ids":["https://openalex.org/I162827531"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5012873906","display_name":"Vivek Yadav","orcid":"https://orcid.org/0000-0001-6145-0281"},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Vivek Yadav","raw_affiliation_strings":["IIT Bombay, Mumbai, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IIT Bombay, Mumbai, India","institution_ids":["https://openalex.org/I162827531"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5071824167","display_name":"Zeeshan Ali","orcid":"https://orcid.org/0000-0003-4660-4822"},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Zeeshan Ali","raw_affiliation_strings":["IIT Bombay, Mumbai, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IIT Bombay, Mumbai, India","institution_ids":["https://openalex.org/I162827531"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5000277012","display_name":"Shalabh Gupta","orcid":"https://orcid.org/0000-0001-5988-9420"},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Shalabh Gupta","raw_affiliation_strings":["IIT Bombay, Mumbai, India"],"raw_orcid":"https://orcid.org/0000-0001-5988-9420","affiliations":[{"raw_affiliation_string":"IIT Bombay, Mumbai, India","institution_ids":["https://openalex.org/I162827531"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I162827531"],"apc_list":null,"apc_paid":null,"fwci":0.5838,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.69266266,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"28","issue":"3","first_page":"714","last_page":"725"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9976999759674072,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.996399998664856,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.8413274884223938},{"id":"https://openalex.org/keywords/dpll-algorithm","display_name":"DPLL algorithm","score":0.8069844245910645},{"id":"https://openalex.org/keywords/settling-time","display_name":"Settling time","score":0.7400894165039062},{"id":"https://openalex.org/keywords/control-theory","display_name":"Control theory (sociology)","score":0.562523603439331},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5414896011352539},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.46956562995910645},{"id":"https://openalex.org/keywords/direct-digital-synthesizer","display_name":"Direct digital synthesizer","score":0.46110305190086365},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4485885500907898},{"id":"https://openalex.org/keywords/frequency-synthesizer","display_name":"Frequency synthesizer","score":0.4404706656932831},{"id":"https://openalex.org/keywords/phase-frequency-detector","display_name":"Phase frequency detector","score":0.4305305480957031},{"id":"https://openalex.org/keywords/loop","display_name":"Loop (graph theory)","score":0.4183991551399231},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.25640225410461426},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.2354462444782257},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.22529923915863037},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.18420076370239258},{"id":"https://openalex.org/keywords/step-response","display_name":"Step response","score":0.1645185649394989},{"id":"https://openalex.org/keywords/charge-pump","display_name":"Charge pump","score":0.10217642784118652},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.08512139320373535}],"concepts":[{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.8413274884223938},{"id":"https://openalex.org/C143936061","wikidata":"https://www.wikidata.org/wiki/Q2030088","display_name":"DPLL algorithm","level":4,"score":0.8069844245910645},{"id":"https://openalex.org/C14781684","wikidata":"https://www.wikidata.org/wiki/Q3983320","display_name":"Settling time","level":3,"score":0.7400894165039062},{"id":"https://openalex.org/C47446073","wikidata":"https://www.wikidata.org/wiki/Q5165890","display_name":"Control theory (sociology)","level":3,"score":0.562523603439331},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5414896011352539},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.46956562995910645},{"id":"https://openalex.org/C166089067","wikidata":"https://www.wikidata.org/wiki/Q1227465","display_name":"Direct digital synthesizer","level":5,"score":0.46110305190086365},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4485885500907898},{"id":"https://openalex.org/C182099602","wikidata":"https://www.wikidata.org/wiki/Q2660678","display_name":"Frequency synthesizer","level":4,"score":0.4404706656932831},{"id":"https://openalex.org/C2776158855","wikidata":"https://www.wikidata.org/wiki/Q2085341","display_name":"Phase frequency detector","level":5,"score":0.4305305480957031},{"id":"https://openalex.org/C184670325","wikidata":"https://www.wikidata.org/wiki/Q512604","display_name":"Loop (graph theory)","level":2,"score":0.4183991551399231},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.25640225410461426},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.2354462444782257},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.22529923915863037},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.18420076370239258},{"id":"https://openalex.org/C160030872","wikidata":"https://www.wikidata.org/wiki/Q2142864","display_name":"Step response","level":2,"score":0.1645185649394989},{"id":"https://openalex.org/C114825011","wikidata":"https://www.wikidata.org/wiki/Q440704","display_name":"Charge pump","level":4,"score":0.10217642784118652},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.08512139320373535},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C133731056","wikidata":"https://www.wikidata.org/wiki/Q4917288","display_name":"Control engineering","level":1,"score":0.0},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C2775924081","wikidata":"https://www.wikidata.org/wiki/Q55608371","display_name":"Control (management)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2019.2956100","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2019.2956100","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320308258","display_name":"Qualcomm","ror":"https://ror.org/002zrf773"},{"id":"https://openalex.org/F4320320722","display_name":"Indian Space Research Organisation","ror":"https://ror.org/00cwrns71"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":33,"referenced_works":["https://openalex.org/W1552094772","https://openalex.org/W1666349805","https://openalex.org/W1981315165","https://openalex.org/W1988318309","https://openalex.org/W1989376602","https://openalex.org/W1995052593","https://openalex.org/W1997287970","https://openalex.org/W2020846474","https://openalex.org/W2023401960","https://openalex.org/W2036186630","https://openalex.org/W2057532062","https://openalex.org/W2090004819","https://openalex.org/W2115662638","https://openalex.org/W2132543896","https://openalex.org/W2142610168","https://openalex.org/W2163268258","https://openalex.org/W2195134145","https://openalex.org/W2294146801","https://openalex.org/W2338238174","https://openalex.org/W2342426112","https://openalex.org/W2344226595","https://openalex.org/W2559073178","https://openalex.org/W2560680290","https://openalex.org/W2565866967","https://openalex.org/W2573263734","https://openalex.org/W2624563526","https://openalex.org/W2758621295","https://openalex.org/W2768747233","https://openalex.org/W2894291793","https://openalex.org/W2901368319","https://openalex.org/W2921338194","https://openalex.org/W4240096133","https://openalex.org/W6760617617"],"related_works":["https://openalex.org/W2043438372","https://openalex.org/W2350523680","https://openalex.org/W2351625286","https://openalex.org/W2085299594","https://openalex.org/W2078991038","https://openalex.org/W3150920887","https://openalex.org/W2605275718","https://openalex.org/W2540964592","https://openalex.org/W1975545773","https://openalex.org/W2376436439"],"abstract_inverted_index":{"The":[0,47,109],"enhancement":[1],"in":[2,57,98,164],"the":[3,51,103,113,118,144,165],"settling":[4,31,52,126],"response":[5,53],"of":[6,106,112,122,138,147,157],"frequency":[7,21,125,137],"synthesizers":[8],"would":[9],"open":[10],"up":[11],"prospects":[12],"for":[13,28],"new":[14],"applications":[15],"such":[16],"as":[17,160],"spread":[18],"spectra":[19],"and":[20,71,76],"hopping":[22],"systems.":[23],"Toward":[24],"deriving":[25],"a":[26,29,35,66,78,134,161],"methodology":[27],"fast":[30],"response,":[32],"we":[33],"present":[34],"switched-loop":[36],"digital":[37,81],"phase":[38,63,150],"locked":[39],"loop":[40],"(DPLL)":[41],"incorporating":[42],"an":[43,153],"integral-derivative":[44],"controller-based":[45],"subsystem.":[46],"dominant":[48],"features":[49],"accelerating":[50],"with":[54,65,87,102],"low":[55],"jitters":[56],"this":[58],"DPLL":[59,93],"are:":[60],"1)":[61],"hybrid":[62],"detection":[64],"state":[67],"machine":[68],"using":[69,133],"differential":[70],"double":[72],"integration":[73],"filtering":[74],"effect":[75],"2)":[77],"time-interleaved":[79],"direct":[80],"synthesizer":[82],"(DDS)-based":[83],"digital-to-time":[84],"converter":[85],"(DTC)":[86],"stable-edge":[88],"sampling.":[89],"A":[90],"5-GHz":[91],"fractional-N":[92],"(FNDPLL)":[94],"has":[95],"been":[96],"implemented":[97,114],"CMOS":[99],"65-nm-LL":[100],"technology":[101],"proposed":[104],"technique":[105],"loop-order":[107],"switching.":[108],"measured":[110],"results":[111],"FNDPLL":[115],"highlight":[116],"that":[117],"system":[119],"is":[120],"capable":[121],"fastest":[123],"reported":[124],"to":[127],"\u00b125-ppm":[128],"error":[129],"within":[130],"1.5":[131],"\u03bcs,":[132],"reference":[135],"clock":[136],"100":[139],"MHz.":[140],"With":[141],"one-time":[142],"calibration,":[143],"downsampled":[145],"output":[146],"DDS":[148],"array-based":[149],"interpolator":[151],"achieves":[152],"integral":[154],"nonlinearity":[155],"(INL)":[156],"0.25":[158],"ps,":[159],"fractional":[162],"divider":[163],"loop.":[166]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}