{"id":"https://openalex.org/W2999380330","doi":"https://doi.org/10.1109/tvlsi.2019.2955933","title":"Gain-Cell Embedded DRAMs: Modeling and Design Space","display_name":"Gain-Cell Embedded DRAMs: Modeling and Design Space","publication_year":2020,"publication_date":"2020-01-07","ids":{"openalex":"https://openalex.org/W2999380330","doi":"https://doi.org/10.1109/tvlsi.2019.2955933","mag":"2999380330"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2019.2955933","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2019.2955933","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"http://infoscience.epfl.ch/record/276578","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5078908633","display_name":"Andrea Bonetti","orcid":"https://orcid.org/0000-0002-0135-5095"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":true,"raw_author_name":"Andrea Bonetti","raw_affiliation_strings":["Telecommunications Circuits Laboratory (TCL), \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), Lausanne, Switzerland"],"raw_orcid":"https://orcid.org/0000-0002-0135-5095","affiliations":[{"raw_affiliation_string":"Telecommunications Circuits Laboratory (TCL), \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5030091052","display_name":"Roman Golman","orcid":"https://orcid.org/0000-0002-1215-5603"},"institutions":[{"id":"https://openalex.org/I13955877","display_name":"Bar-Ilan University","ror":"https://ror.org/03kgsv495","country_code":"IL","type":"education","lineage":["https://openalex.org/I13955877"]}],"countries":["IL"],"is_corresponding":false,"raw_author_name":"Roman Golman","raw_affiliation_strings":["Faculty of Engineering, Bar-Ilan University, Ramat Gan, Israel"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Faculty of Engineering, Bar-Ilan University, Ramat Gan, Israel","institution_ids":["https://openalex.org/I13955877"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5034618529","display_name":"Robert Giterman","orcid":"https://orcid.org/0000-0002-1410-4746"},"institutions":[{"id":"https://openalex.org/I13955877","display_name":"Bar-Ilan University","ror":"https://ror.org/03kgsv495","country_code":"IL","type":"education","lineage":["https://openalex.org/I13955877"]}],"countries":["IL"],"is_corresponding":false,"raw_author_name":"Robert Giterman","raw_affiliation_strings":["Faculty of Engineering, Bar-Ilan University, Ramat Gan, Israel"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Faculty of Engineering, Bar-Ilan University, Ramat Gan, Israel","institution_ids":["https://openalex.org/I13955877"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5026444183","display_name":"Adam Teman","orcid":"https://orcid.org/0000-0002-8233-4711"},"institutions":[{"id":"https://openalex.org/I13955877","display_name":"Bar-Ilan University","ror":"https://ror.org/03kgsv495","country_code":"IL","type":"education","lineage":["https://openalex.org/I13955877"]}],"countries":["IL"],"is_corresponding":false,"raw_author_name":"Adam Teman","raw_affiliation_strings":["Faculty of Engineering, Bar-Ilan University, Ramat Gan, Israel"],"raw_orcid":"https://orcid.org/0000-0002-8233-4711","affiliations":[{"raw_affiliation_string":"Faculty of Engineering, Bar-Ilan University, Ramat Gan, Israel","institution_ids":["https://openalex.org/I13955877"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5059133771","display_name":"Andreas Burg","orcid":"https://orcid.org/0000-0002-7270-5558"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Andreas Burg","raw_affiliation_strings":["Telecommunications Circuits Laboratory (TCL), \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), Lausanne, Switzerland"],"raw_orcid":"https://orcid.org/0000-0002-7270-5558","affiliations":[{"raw_affiliation_string":"Telecommunications Circuits Laboratory (TCL), \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5078908633"],"corresponding_institution_ids":["https://openalex.org/I5124864"],"apc_list":null,"apc_paid":null,"fwci":0.9716,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":{"value":0.77014725,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":"28","issue":"3","first_page":"646","last_page":"659"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.7042987942695618},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.6043224930763245},{"id":"https://openalex.org/keywords/dynamic-random-access-memory","display_name":"Dynamic random-access memory","score":0.5303469300270081},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5255305171012878},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5139452815055847},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.4585736393928528},{"id":"https://openalex.org/keywords/random-access","display_name":"Random access","score":0.43755853176116943},{"id":"https://openalex.org/keywords/context","display_name":"Context (archaeology)","score":0.431674987077713},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4101380407810211},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4080323576927185},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.3177185654640198},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2168877124786377},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.21321845054626465},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.17940443754196167},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.13808009028434753}],"concepts":[{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.7042987942695618},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.6043224930763245},{"id":"https://openalex.org/C118702147","wikidata":"https://www.wikidata.org/wiki/Q189396","display_name":"Dynamic random-access memory","level":3,"score":0.5303469300270081},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5255305171012878},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5139452815055847},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.4585736393928528},{"id":"https://openalex.org/C101722063","wikidata":"https://www.wikidata.org/wiki/Q218825","display_name":"Random access","level":2,"score":0.43755853176116943},{"id":"https://openalex.org/C2779343474","wikidata":"https://www.wikidata.org/wiki/Q3109175","display_name":"Context (archaeology)","level":2,"score":0.431674987077713},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4101380407810211},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4080323576927185},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.3177185654640198},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2168877124786377},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21321845054626465},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.17940443754196167},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.13808009028434753},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/tvlsi.2019.2955933","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2019.2955933","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},{"id":"pmh:oai:infoscience.epfl.ch:276578","is_oa":true,"landing_page_url":"http://infoscience.epfl.ch/record/276578","pdf_url":null,"source":{"id":"https://openalex.org/S4306400487","display_name":"Infoscience (Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://infoscience.epfl.ch/record/276578","raw_type":"Text"}],"best_oa_location":{"id":"pmh:oai:infoscience.epfl.ch:276578","is_oa":true,"landing_page_url":"http://infoscience.epfl.ch/record/276578","pdf_url":null,"source":{"id":"https://openalex.org/S4306400487","display_name":"Infoscience (Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://infoscience.epfl.ch/record/276578","raw_type":"Text"},"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320320947","display_name":"German-Israeli Foundation for Scientific Research and Development","ror":"https://ror.org/00tntzp09"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":29,"referenced_works":["https://openalex.org/W1971936677","https://openalex.org/W2039742886","https://openalex.org/W2082055514","https://openalex.org/W2084514439","https://openalex.org/W2093163564","https://openalex.org/W2097346754","https://openalex.org/W2100799944","https://openalex.org/W2131434692","https://openalex.org/W2147657366","https://openalex.org/W2150073849","https://openalex.org/W2161091390","https://openalex.org/W2164586147","https://openalex.org/W2216509856","https://openalex.org/W2289252105","https://openalex.org/W2733005606","https://openalex.org/W2745056282","https://openalex.org/W2754347129","https://openalex.org/W2789835201","https://openalex.org/W2800944932","https://openalex.org/W2887937160","https://openalex.org/W2914665169","https://openalex.org/W2963255460","https://openalex.org/W3090521109","https://openalex.org/W3143002681","https://openalex.org/W3145579537","https://openalex.org/W4243164749","https://openalex.org/W6671281726","https://openalex.org/W6679139576","https://openalex.org/W6759171872"],"related_works":["https://openalex.org/W2518930778","https://openalex.org/W2979599569","https://openalex.org/W3007039213","https://openalex.org/W3094611732","https://openalex.org/W2533585248","https://openalex.org/W2559795407","https://openalex.org/W2944414554","https://openalex.org/W3009022466","https://openalex.org/W2127643145","https://openalex.org/W2186356227"],"abstract_inverted_index":{"Among":[0],"the":[1,59,68,71,77,86,109,131,159,172,175,180,183,211,239,250,260],"different":[2,205],"types":[3],"of":[4,61,70,73,89,103,111,120,143,161,182,194,216,238,255],"dynamic":[5],"random-access":[6,23],"memories":[7,75,104],"(DRAMs),":[8],"gain-cell":[9],"embedded":[10],"DRAM":[11],"(GC-eDRAM)":[12],"is":[13,188,226,246],"a":[14,35,117,191,200,217,221,229],"compact,":[15],"low-power,":[16],"and":[17,48,141,153,156,208,257],"CMOS-compatible":[18],"alternative":[19],"to":[20,93,150,179,248],"conventional":[21],"static":[22],"memory":[24,29,138,154,206],"(SRAM).":[25],"GC-eDRAM":[26,127,218],"achieves":[27],"high":[28],"density,":[30],"as":[31,43,45,83,85,164,166,171],"it":[32,157],"relies":[33,63],"on":[34,64,259],"storage":[36],"cell":[37],"that":[38,49,135],"can":[39,50],"be":[40,51,94],"implemented":[41],"with":[42,190,228],"few":[44],"two":[46],"transistors":[47],"fabricated":[52,219],"without":[53],"additional":[54],"process":[55,225,236],"steps.":[56],"However,":[57],"since":[58],"performance":[60,72],"GC-eDRAMs":[62],"many":[65],"interdependent":[66],"variables,":[67],"optimization":[69,254],"these":[74],"for":[76,108,204],"integration":[78],"into":[79],"their":[80],"hosting":[81],"system,":[82],"well":[84,165],"design":[87,114,253,263],"investigation":[88],"future":[90],"GC-eDRAMs,":[91,256],"proves":[92],"highly":[95],"complex":[96],"tasks.":[97],"In":[98,122],"this":[99,112,123],"context,":[100],"modeling":[101,128,133,244],"tools":[102],"are":[105,265],"key":[106],"enablers":[107],"exploration":[110],"large":[113],"space":[115],"in":[116,174,199,220,252],"short":[118],"amount":[119],"time.":[121],"article,":[124],"we":[125],"present":[126],"tool":[129,134,146,245],"(GEMTOO),":[130],"first":[132],"estimates":[136],"timing,":[137],"availability,":[139],"bandwidth,":[140],"area":[142],"GC-eDRAMs.":[144],"The":[145,186,241],"considers":[147],"parameters":[148],"related":[149],"technology,":[151],"circuits,":[152],"architecture,":[155],"enables":[158],"evaluation":[160],"architectural":[162],"transformations":[163],"advanced":[167],"transistor-level":[168],"effects,":[169],"such":[170],"increase":[173],"access":[176],"delay":[177],"due":[178],"deterioration":[181],"stored":[184],"data.":[185],"timing":[187],"estimated":[189,227],"maximum":[192],"deviation":[193,231],"15%":[195],"from":[196],"postlayout":[197],"simulations":[198],"28-nm":[201,222],"FD-SOI":[202],"technology":[203],"sizes":[207],"architectures.":[209],"Moreover,":[210],"measured":[212],"random":[213,235],"cycle":[214],"frequency":[215],"CMOS":[223],"bulk":[224],"9%":[230],"when":[232],"considering":[233],"6-sigma":[234],"variations":[237],"bitcells.":[240],"proposed":[242],"GEMTOO":[243],"used":[247],"show":[249],"intricacies":[251],"based":[258],"results,":[261],"optimal":[262],"practices":[264],"derived.":[266]},"counts_by_year":[{"year":2026,"cited_by_count":2},{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1}],"updated_date":"2026-05-03T08:25:01.440150","created_date":"2025-10-10T00:00:00"}