{"id":"https://openalex.org/W2984242728","doi":"https://doi.org/10.1109/tvlsi.2019.2947639","title":"POLAR: A Pipelined/Overlapped FPGA-Based LSTM Accelerator","display_name":"POLAR: A Pipelined/Overlapped FPGA-Based LSTM Accelerator","publication_year":2019,"publication_date":"2019-11-01","ids":{"openalex":"https://openalex.org/W2984242728","doi":"https://doi.org/10.1109/tvlsi.2019.2947639","mag":"2984242728"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2019.2947639","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2019.2947639","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5078467314","display_name":"Erfan Bank Tavakoli","orcid":"https://orcid.org/0000-0002-3248-9301"},"institutions":[{"id":"https://openalex.org/I23946033","display_name":"University of Tehran","ror":"https://ror.org/05vf56z40","country_code":"IR","type":"education","lineage":["https://openalex.org/I23946033"]}],"countries":["IR"],"is_corresponding":true,"raw_author_name":"Erfan Bank-Tavakoli","raw_affiliation_strings":["School of Electrical and Computer Engineering, College of Engineering, University of Tehran, Tehran, Iran"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, College of Engineering, University of Tehran, Tehran, Iran","institution_ids":["https://openalex.org/I23946033"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061470852","display_name":"Seyed Abolfazl Ghasemzadeh","orcid":"https://orcid.org/0000-0001-7111-5778"},"institutions":[{"id":"https://openalex.org/I23946033","display_name":"University of Tehran","ror":"https://ror.org/05vf56z40","country_code":"IR","type":"education","lineage":["https://openalex.org/I23946033"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"Seyed Abolfazl Ghasemzadeh","raw_affiliation_strings":["School of Electrical and Computer Engineering, College of Engineering, University of Tehran, Tehran, Iran"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, College of Engineering, University of Tehran, Tehran, Iran","institution_ids":["https://openalex.org/I23946033"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5042809860","display_name":"Mehdi Kamal","orcid":"https://orcid.org/0000-0001-7098-6440"},"institutions":[{"id":"https://openalex.org/I23946033","display_name":"University of Tehran","ror":"https://ror.org/05vf56z40","country_code":"IR","type":"education","lineage":["https://openalex.org/I23946033"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"Mehdi Kamal","raw_affiliation_strings":["School of Electrical and Computer Engineering, College of Engineering, University of Tehran, Tehran, Iran"],"raw_orcid":"https://orcid.org/0000-0001-7098-6440","affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, College of Engineering, University of Tehran, Tehran, Iran","institution_ids":["https://openalex.org/I23946033"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5074063358","display_name":"Ali Afzali\u2010Kusha","orcid":"https://orcid.org/0000-0001-8614-2007"},"institutions":[{"id":"https://openalex.org/I23946033","display_name":"University of Tehran","ror":"https://ror.org/05vf56z40","country_code":"IR","type":"education","lineage":["https://openalex.org/I23946033"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"Ali Afzali-Kusha","raw_affiliation_strings":["School of Electrical and Computer Engineering, College of Engineering, University of Tehran, Tehran, Iran"],"raw_orcid":"https://orcid.org/0000-0001-8614-2007","affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, College of Engineering, University of Tehran, Tehran, Iran","institution_ids":["https://openalex.org/I23946033"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5044650311","display_name":"Massoud Pedram","orcid":"https://orcid.org/0000-0002-2677-7307"},"institutions":[{"id":"https://openalex.org/I1174212","display_name":"University of Southern California","ror":"https://ror.org/03taz7m60","country_code":"US","type":"education","lineage":["https://openalex.org/I1174212"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Massoud Pedram","raw_affiliation_strings":["University of Southern California, Los Angeles, USA"],"raw_orcid":"https://orcid.org/0000-0002-2677-7307","affiliations":[{"raw_affiliation_string":"University of Southern California, Los Angeles, USA","institution_ids":["https://openalex.org/I1174212"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5078467314"],"corresponding_institution_ids":["https://openalex.org/I23946033"],"apc_list":null,"apc_paid":null,"fwci":8.6382,"has_fulltext":false,"cited_by_count":52,"citation_normalized_percentile":{"value":0.98417321,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":100},"biblio":{"volume":"28","issue":"3","first_page":"838","last_page":"842"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10201","display_name":"Speech Recognition and Synthesis","score":0.9926999807357788,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11269","display_name":"Algorithms and Data Compression","score":0.9861999750137329,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/datapath","display_name":"Datapath","score":0.9073390960693359},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8063294887542725},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7657318115234375},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.576256513595581},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5250049829483032},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5082702040672302},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.49737265706062317},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.4884437620639801},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.43813619017601013},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.382647305727005}],"concepts":[{"id":"https://openalex.org/C2781198647","wikidata":"https://www.wikidata.org/wiki/Q1633673","display_name":"Datapath","level":2,"score":0.9073390960693359},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8063294887542725},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7657318115234375},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.576256513595581},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5250049829483032},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5082702040672302},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.49737265706062317},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.4884437620639801},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.43813619017601013},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.382647305727005},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2019.2947639","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2019.2947639","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W1689711448","https://openalex.org/W1964812476","https://openalex.org/W1969494847","https://openalex.org/W2016053056","https://openalex.org/W2064675550","https://openalex.org/W2100649405","https://openalex.org/W2116261113","https://openalex.org/W2143612262","https://openalex.org/W2163605009","https://openalex.org/W2177436562","https://openalex.org/W2585720638","https://openalex.org/W2588448445","https://openalex.org/W2589086007","https://openalex.org/W2757698722","https://openalex.org/W2891504940","https://openalex.org/W2904469955","https://openalex.org/W2964033223","https://openalex.org/W4297699616","https://openalex.org/W6684191040","https://openalex.org/W6685823913","https://openalex.org/W6764473562"],"related_works":["https://openalex.org/W2113434540","https://openalex.org/W2140956115","https://openalex.org/W2110265185","https://openalex.org/W3146360095","https://openalex.org/W2058686619","https://openalex.org/W2534209688","https://openalex.org/W4230329051","https://openalex.org/W4231072303","https://openalex.org/W1580556151","https://openalex.org/W2154356865"],"abstract_inverted_index":{"In":[0],"this":[1,46],"brief,":[2],"a":[3,120],"low":[4,60],"resource":[5,61,79],"utilization":[6,62,80],"field-programmable":[7],"gate":[8],"array":[9],"(FPGA)-based":[10],"long":[11],"short-term":[12],"memory":[13,51],"(LSTM)":[14],"network":[15,135],"architecture":[16,25,47,89,110,128,148,173],"for":[17,53],"accelerating":[18],"the":[19,36,39,43,55,78,84,87,92,99,105,109,126,143,146,183],"inference":[20],"phase":[21],"is":[22,129,179],"presented.":[23],"The":[24,123],"has":[26],"low-power":[27],"and":[28,41,63,159,167],"high-speed":[29],"features":[30],"that":[31],"are":[32],"achieved":[33],"through":[34],"overlapping":[35],"timing":[37],"of":[38,86,101,107,114,125,139],"operations":[40],"pipelining":[42],"datapath.":[44],"Moreover,":[45],"requires":[48],"negligible":[49],"internal":[50],"size":[52],"storing":[54],"intermediate":[56],"data":[57],"leading":[58],"to":[59,117,151],"simple":[64,121],"routing,":[65],"which":[66,178],"provides":[67,149],"lower":[68],"interconnect":[69],"delay":[70],"(higher":[71],"operating":[72],"frequency).":[73],"A":[74],"designer":[75],"may":[76],"adjust":[77],"(as":[81],"well":[82],"as":[83],"latency)":[85],"proposed":[88,127,147,172],"readily":[90],"at":[91,175],"register-transfer":[93],"level":[94],"(RTL)":[95],"design":[96],"by":[97,131],"adjusting":[98],"amount":[100],"parallelization.":[102],"This":[103],"makes":[104],"process":[106],"mapping":[108],"onto":[111],"different":[112,137],"types":[113,138],"FPGAs,":[115],"subject":[116],"defined":[118],"constraints,":[119],"one.":[122],"efficacy":[124],"assessed":[130],"implementing":[132],"an":[133],"LSTM":[134],"on":[136],"FPGAs.":[140],"Compared":[141],"with":[142],"recent":[144],"works,":[145],"up":[150],"about":[152],"1.6x":[153],",":[154,156,158],"43.6x":[155],"21.9x":[157],"114.5x":[160],"improvements":[161],"in":[162],"frequency,":[163],"power":[164],"efficiency,":[165],"GOP/s,":[166,177],"GOP/s/W,":[168],"respectively.":[169],"Finally,":[170],"our":[171],"operates":[174],"17.64":[176],"2.31":[180],"faster":[181],"than":[182],"best":[184],"previously":[185],"reported":[186],"results.":[187]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":5},{"year":2023,"cited_by_count":10},{"year":2022,"cited_by_count":10},{"year":2021,"cited_by_count":16},{"year":2020,"cited_by_count":8},{"year":2019,"cited_by_count":1}],"updated_date":"2026-04-30T09:15:22.047038","created_date":"2025-10-10T00:00:00"}
