{"id":"https://openalex.org/W2982335319","doi":"https://doi.org/10.1109/tvlsi.2019.2947183","title":"Maintaining Scalability of Test Generation Using Multicore Shared Memory Systems","display_name":"Maintaining Scalability of Test Generation Using Multicore Shared Memory Systems","publication_year":2019,"publication_date":"2019-10-29","ids":{"openalex":"https://openalex.org/W2982335319","doi":"https://doi.org/10.1109/tvlsi.2019.2947183","mag":"2982335319"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2019.2947183","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2019.2947183","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://zenodo.org/record/3518065","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5019013823","display_name":"Stavros Hadjitheophanous","orcid":"https://orcid.org/0000-0002-9029-2101"},"institutions":[{"id":"https://openalex.org/I34771391","display_name":"University of Cyprus","ror":"https://ror.org/02qjrjx09","country_code":"CY","type":"education","lineage":["https://openalex.org/I34771391"]}],"countries":["CY"],"is_corresponding":false,"raw_author_name":"Stavros Hadjitheophanous","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Cyprus, Nicosia, Cyprus","KIOS Research and Innovation Center of Excellence, University of Cyprus, Nicosia, Cyprus"],"raw_orcid":"https://orcid.org/0000-0002-9029-2101","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Cyprus, Nicosia, Cyprus","institution_ids":["https://openalex.org/I34771391"]},{"raw_affiliation_string":"KIOS Research and Innovation Center of Excellence, University of Cyprus, Nicosia, Cyprus","institution_ids":["https://openalex.org/I34771391"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5077460840","display_name":"Stelios Neophytou","orcid":"https://orcid.org/0000-0001-5728-6845"},"institutions":[{"id":"https://openalex.org/I17389662","display_name":"University of Nicosia","ror":"https://ror.org/04v18t651","country_code":"CY","type":"education","lineage":["https://openalex.org/I17389662"]}],"countries":["CY"],"is_corresponding":false,"raw_author_name":"Stelios N. Neophytou","raw_affiliation_strings":["Department of Engineering, University of Nicosia, Nicosia, Cyprus"],"raw_orcid":"https://orcid.org/0000-0001-5728-6845","affiliations":[{"raw_affiliation_string":"Department of Engineering, University of Nicosia, Nicosia, Cyprus","institution_ids":["https://openalex.org/I17389662"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5063130153","display_name":"Maria K. Michael","orcid":"https://orcid.org/0000-0002-1943-6547"},"institutions":[{"id":"https://openalex.org/I34771391","display_name":"University of Cyprus","ror":"https://ror.org/02qjrjx09","country_code":"CY","type":"education","lineage":["https://openalex.org/I34771391"]}],"countries":["CY"],"is_corresponding":false,"raw_author_name":"Maria K. Michael","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Cyprus, Nicosia, Cyprus","KIOS Research and Innovation Center of Excellence, University of Cyprus, Nicosia, Cyprus"],"raw_orcid":"https://orcid.org/0000-0002-1943-6547","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Cyprus, Nicosia, Cyprus","institution_ids":["https://openalex.org/I34771391"]},{"raw_affiliation_string":"KIOS Research and Innovation Center of Excellence, University of Cyprus, Nicosia, Cyprus","institution_ids":["https://openalex.org/I34771391"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.13851608,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"28","issue":"2","first_page":"553","last_page":"564"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10743","display_name":"Software Testing and Debugging Techniques","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/1712","display_name":"Software"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.8011044263839722},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7596945762634277},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.7268372774124146},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.6566133499145508},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6375935673713684},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.6117929220199585},{"id":"https://openalex.org/keywords/workload","display_name":"Workload","score":0.6076247096061707},{"id":"https://openalex.org/keywords/fault-coverage","display_name":"Fault coverage","score":0.5165914297103882},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.342265784740448},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3242776393890381},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.10970288515090942}],"concepts":[{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.8011044263839722},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7596945762634277},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.7268372774124146},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.6566133499145508},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6375935673713684},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.6117929220199585},{"id":"https://openalex.org/C2778476105","wikidata":"https://www.wikidata.org/wiki/Q628539","display_name":"Workload","level":2,"score":0.6076247096061707},{"id":"https://openalex.org/C126953365","wikidata":"https://www.wikidata.org/wiki/Q5438152","display_name":"Fault coverage","level":3,"score":0.5165914297103882},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.342265784740448},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3242776393890381},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.10970288515090942},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/tvlsi.2019.2947183","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2019.2947183","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},{"id":"pmh:oai:zenodo.org:3518065","is_oa":true,"landing_page_url":"https://zenodo.org/record/3518065","pdf_url":null,"source":{"id":"https://openalex.org/S4306400562","display_name":"Zenodo (CERN European Organization for Nuclear Research)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I67311998","host_organization_name":"European Organization for Nuclear Research","host_organization_lineage":["https://openalex.org/I67311998"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1-12","raw_type":"info:eu-repo/semantics/article"}],"best_oa_location":{"id":"pmh:oai:zenodo.org:3518065","is_oa":true,"landing_page_url":"https://zenodo.org/record/3518065","pdf_url":null,"source":{"id":"https://openalex.org/S4306400562","display_name":"Zenodo (CERN European Organization for Nuclear Research)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I67311998","host_organization_name":"European Organization for Nuclear Research","host_organization_lineage":["https://openalex.org/I67311998"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1-12","raw_type":"info:eu-repo/semantics/article"},"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G3638315080","display_name":null,"funder_award_id":"10.13039/100010661","funder_id":"https://openalex.org/F4320332999","funder_display_name":"Horizon 2020 Framework Programme"}],"funders":[{"id":"https://openalex.org/F4320332999","display_name":"Horizon 2020 Framework Programme","ror":"https://ror.org/00k4n6c32"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":33,"referenced_works":["https://openalex.org/W1531040488","https://openalex.org/W1575233213","https://openalex.org/W1595368737","https://openalex.org/W1961788500","https://openalex.org/W1968292327","https://openalex.org/W1982628661","https://openalex.org/W1988641939","https://openalex.org/W2009690023","https://openalex.org/W2034030717","https://openalex.org/W2043080135","https://openalex.org/W2061411509","https://openalex.org/W2063193331","https://openalex.org/W2068324641","https://openalex.org/W2073590490","https://openalex.org/W2089540425","https://openalex.org/W2090601222","https://openalex.org/W2097349963","https://openalex.org/W2116499908","https://openalex.org/W2125029377","https://openalex.org/W2134895826","https://openalex.org/W2135615172","https://openalex.org/W2154508111","https://openalex.org/W2154934646","https://openalex.org/W2156747864","https://openalex.org/W2612666615","https://openalex.org/W2801379610","https://openalex.org/W2858511667","https://openalex.org/W2868194494","https://openalex.org/W2888957887","https://openalex.org/W3035062237","https://openalex.org/W3148278272","https://openalex.org/W4231973520","https://openalex.org/W6737663505"],"related_works":["https://openalex.org/W2091833418","https://openalex.org/W2913077774","https://openalex.org/W2021253405","https://openalex.org/W4256030018","https://openalex.org/W2145089576","https://openalex.org/W3012895752","https://openalex.org/W1986228509","https://openalex.org/W2147400189","https://openalex.org/W2340957901","https://openalex.org/W1991935474"],"abstract_inverted_index":{"Taking":[0],"advantage":[1],"of":[2,76,174,178],"multicore":[3,50],"architectures":[4],"can":[5],"provide":[6],"significant":[7],"improvement":[8],"for":[9,42,57,102,180],"many":[10],"design":[11],"automation":[12],"problems.":[13],"However,":[14],"the":[15,103,110,121,143,149,152,159,167,171,176],"parallelization":[16],"procedure":[17,106],"introduces":[18],"challenges,":[19],"such":[20],"as":[21],"workload":[22,169],"duplication,":[23],"limited":[24],"search":[25],"space":[26],"exploration,":[27],"and":[28,60,170],"race":[29],"contention":[30],"among":[31],"different":[32,74],"threads.":[33],"In":[34],"this":[35],"article,":[36],"we":[37],"propose":[38],"a":[39,67,73,80],"parallel":[40],"framework":[41,65,123],"automatic":[43],"test":[44,54,81,111,153],"pattern":[45],"generation":[46,55,83],"using":[47],"shared":[48],"memory":[49],"systems":[51],"that":[52],"support":[53],"(TG)":[56],"both":[58],"single-detect":[59],"multiple-detect":[61,126,160],"fault":[62,127,182],"models.":[63],"The":[64,133],"follows":[66],"two-epoch":[68],"approach,":[69],"each":[70,95,181],"focusing":[71],"on":[72],"category":[75],"faults,":[77],"during":[78],"which":[79],"seed":[82],"is":[84,117,156],"followed":[85],"by":[86],"compatibility":[87],"merging.":[88,184],"Various":[89],"optimization":[90],"techniques":[91],"are":[92,164],"incorporated":[93],"in":[94],"epoch,":[96],"designed":[97],"to":[98,124],"achieve":[99],"higher":[100],"speedup":[101,139],"overall":[104],"TG":[105],"without":[107,129],"impacting":[108],"much":[109],"set":[112],"size.":[113],"A":[114],"cluster-based":[115],"approach":[116],"also":[118],"presented,":[119],"extending":[120],"proposed":[122],"consider":[125],"models":[128],"affecting":[130],"its":[131],"efficiency.":[132],"obtained":[134],"experimental":[135],"results":[136],"demonstrate":[137],"increased":[138,168],"rates":[140],"compared":[141],"with":[142],"state-of-the-art":[144],"multicore-based":[145],"tools":[146],"while,":[147],"at":[148],"same":[150],"time,":[151],"inflation":[154],"problem":[155],"restrained.":[157],"For":[158],"extension,":[161],"these":[162],"properties":[163],"maintained":[165],"despite":[166],"additional":[172],"constraint":[173],"retaining":[175],"number":[177],"detections":[179],"while":[183]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}