{"id":"https://openalex.org/W2981928219","doi":"https://doi.org/10.1109/tvlsi.2019.2946348","title":"The Mesochronous Dual-Clock FIFO Buffer","display_name":"The Mesochronous Dual-Clock FIFO Buffer","publication_year":2019,"publication_date":"2019-10-22","ids":{"openalex":"https://openalex.org/W2981928219","doi":"https://doi.org/10.1109/tvlsi.2019.2946348","mag":"2981928219"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2019.2946348","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2019.2946348","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5087276237","display_name":"Dimitrios Konstantinou","orcid":"https://orcid.org/0000-0001-5742-171X"},"institutions":[{"id":"https://openalex.org/I147962203","display_name":"Democritus University of Thrace","ror":"https://ror.org/03bfqnx40","country_code":"GR","type":"education","lineage":["https://openalex.org/I147962203"]}],"countries":["GR"],"is_corresponding":true,"raw_author_name":"Dimitrios Konstantinou","raw_affiliation_strings":["Electrical and Computer Engineering Department, Democritus University of Thrace, Xanthi, Greece","Electrical & Computer Engineering Department, Democritus University of Thrace, Xanthi, Greece"],"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering Department, Democritus University of Thrace, Xanthi, Greece","institution_ids":["https://openalex.org/I147962203"]},{"raw_affiliation_string":"Electrical & Computer Engineering Department, Democritus University of Thrace, Xanthi, Greece","institution_ids":["https://openalex.org/I147962203"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052539927","display_name":"\u0391\u03bd\u03b1\u03c3\u03c4\u03ac\u03c3\u03b9\u03bf\u03c2 \u03a8\u03b1\u03c1\u03c1\u03ac\u03c2","orcid":"https://orcid.org/0000-0001-6151-9242"},"institutions":[{"id":"https://openalex.org/I147962203","display_name":"Democritus University of Thrace","ror":"https://ror.org/03bfqnx40","country_code":"GR","type":"education","lineage":["https://openalex.org/I147962203"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Anastasios Psarras","raw_affiliation_strings":["Electrical and Computer Engineering Department, Democritus University of Thrace, Xanthi, Greece","Electrical & Computer Engineering Department, Democritus University of Thrace, Xanthi, Greece"],"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering Department, Democritus University of Thrace, Xanthi, Greece","institution_ids":["https://openalex.org/I147962203"]},{"raw_affiliation_string":"Electrical & Computer Engineering Department, Democritus University of Thrace, Xanthi, Greece","institution_ids":["https://openalex.org/I147962203"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5035714231","display_name":"Chrysostomos Nicopoulos","orcid":"https://orcid.org/0000-0001-6389-6068"},"institutions":[{"id":"https://openalex.org/I34771391","display_name":"University of Cyprus","ror":"https://ror.org/02qjrjx09","country_code":"CY","type":"education","lineage":["https://openalex.org/I34771391"]}],"countries":["CY"],"is_corresponding":false,"raw_author_name":"Chrysostomos Nicopoulos","raw_affiliation_strings":["Electrical and Computer Engineering Department, University of Cyprus, Nicosia, Cyprus"],"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering Department, University of Cyprus, Nicosia, Cyprus","institution_ids":["https://openalex.org/I34771391"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5074704256","display_name":"Giorgos Dimitrakopoulos","orcid":"https://orcid.org/0000-0003-3688-7865"},"institutions":[{"id":"https://openalex.org/I147962203","display_name":"Democritus University of Thrace","ror":"https://ror.org/03bfqnx40","country_code":"GR","type":"education","lineage":["https://openalex.org/I147962203"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Giorgos Dimitrakopoulos","raw_affiliation_strings":["Electrical and Computer Engineering Department, Democritus University of Thrace, Xanthi, Greece","Electrical & Computer Engineering Department, Democritus University of Thrace, Xanthi, Greece"],"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering Department, Democritus University of Thrace, Xanthi, Greece","institution_ids":["https://openalex.org/I147962203"]},{"raw_affiliation_string":"Electrical & Computer Engineering Department, Democritus University of Thrace, Xanthi, Greece","institution_ids":["https://openalex.org/I147962203"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5087276237"],"corresponding_institution_ids":["https://openalex.org/I147962203"],"apc_list":null,"apc_paid":null,"fwci":0.8842,"has_fulltext":false,"cited_by_count":14,"citation_normalized_percentile":{"value":0.77280363,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":"28","issue":"1","first_page":"302","last_page":"306"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9947999715805054,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/synchronizing","display_name":"Synchronizing","score":0.7212070226669312},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.7134407758712769},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.7090187072753906},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6930525302886963},{"id":"https://openalex.org/keywords/fifo","display_name":"FIFO (computing and electronics)","score":0.686050534248352},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.5704689621925354},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.5659229755401611},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.5647066831588745},{"id":"https://openalex.org/keywords/timing-failure","display_name":"Timing failure","score":0.5426817536354065},{"id":"https://openalex.org/keywords/clock-synchronization","display_name":"Clock synchronization","score":0.5085934400558472},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.4859286844730377},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.4690167307853699},{"id":"https://openalex.org/keywords/clock-recovery","display_name":"Clock recovery","score":0.4637983441352844},{"id":"https://openalex.org/keywords/clock-drift","display_name":"Clock drift","score":0.45621246099472046},{"id":"https://openalex.org/keywords/cpu-multiplier","display_name":"CPU multiplier","score":0.4498153030872345},{"id":"https://openalex.org/keywords/self-clocking-signal","display_name":"Self-clocking signal","score":0.42441269755363464},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4147006869316101},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.4129827618598938},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.40270841121673584},{"id":"https://openalex.org/keywords/channel","display_name":"Channel (broadcasting)","score":0.17695879936218262},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.13032636046409607},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08382612466812134}],"concepts":[{"id":"https://openalex.org/C162932704","wikidata":"https://www.wikidata.org/wiki/Q1058791","display_name":"Synchronizing","level":3,"score":0.7212070226669312},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.7134407758712769},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.7090187072753906},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6930525302886963},{"id":"https://openalex.org/C2777145635","wikidata":"https://www.wikidata.org/wiki/Q515636","display_name":"FIFO (computing and electronics)","level":2,"score":0.686050534248352},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.5704689621925354},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.5659229755401611},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.5647066831588745},{"id":"https://openalex.org/C104654189","wikidata":"https://www.wikidata.org/wiki/Q7806740","display_name":"Timing failure","level":5,"score":0.5426817536354065},{"id":"https://openalex.org/C129891060","wikidata":"https://www.wikidata.org/wiki/Q1513059","display_name":"Clock synchronization","level":4,"score":0.5085934400558472},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.4859286844730377},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.4690167307853699},{"id":"https://openalex.org/C2779835379","wikidata":"https://www.wikidata.org/wiki/Q2348121","display_name":"Clock recovery","level":4,"score":0.4637983441352844},{"id":"https://openalex.org/C155837451","wikidata":"https://www.wikidata.org/wiki/Q1069144","display_name":"Clock drift","level":5,"score":0.45621246099472046},{"id":"https://openalex.org/C125576049","wikidata":"https://www.wikidata.org/wiki/Q2246273","display_name":"CPU multiplier","level":5,"score":0.4498153030872345},{"id":"https://openalex.org/C171051901","wikidata":"https://www.wikidata.org/wiki/Q2389679","display_name":"Self-clocking signal","level":5,"score":0.42441269755363464},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4147006869316101},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.4129827618598938},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.40270841121673584},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.17695879936218262},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.13032636046409607},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08382612466812134},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.0},{"id":"https://openalex.org/C761482","wikidata":"https://www.wikidata.org/wiki/Q118093","display_name":"Transmission (telecommunications)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2019.2946348","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2019.2946348","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W1544623790","https://openalex.org/W2004400707","https://openalex.org/W2037181413","https://openalex.org/W2050506251","https://openalex.org/W2099034654","https://openalex.org/W2119616711","https://openalex.org/W2125090069","https://openalex.org/W2126647846","https://openalex.org/W2133654314","https://openalex.org/W2136011486","https://openalex.org/W2136692989","https://openalex.org/W2141690700","https://openalex.org/W2347079473","https://openalex.org/W2472281836","https://openalex.org/W2483261519","https://openalex.org/W2615329347","https://openalex.org/W2749961276","https://openalex.org/W2767976779","https://openalex.org/W3145659410","https://openalex.org/W6680198301"],"related_works":["https://openalex.org/W2246178160","https://openalex.org/W2083095101","https://openalex.org/W4248271274","https://openalex.org/W2109520798","https://openalex.org/W2389820945","https://openalex.org/W2357497058","https://openalex.org/W2371965169","https://openalex.org/W1966845705","https://openalex.org/W2411759562","https://openalex.org/W2349480346"],"abstract_inverted_index":{"To":[0],"increase":[1],"system":[2],"composability":[3],"and":[4,91,118,155],"facilitate":[5],"timing":[6],"closure,":[7],"fully":[8],"synchronous":[9],"clocking":[10,16],"is":[11,66,176],"replaced":[12],"by":[13,95,123],"more":[14],"relaxed":[15],"schemes,":[17],"such":[18,62,137],"as":[19],"mesochronous":[20,33,80,141,170],"clocking.":[21],"Under":[22],"this":[23,74],"regime,":[24],"the":[25,28,36,43,48,51,100,105,116,119,132,139,160,166,173],"modules":[26],"at":[27],"two":[29],"ends":[30],"of":[31,50,103],"a":[32,78,124,152,180],"interface":[34],"receive":[35],"same":[37,44],"clock":[38,45,53,64,89],"signal,":[39],"thus":[40],"operating":[41,134],"under":[42],"frequency,":[46],"but":[47],"edges":[49],"arriving":[52],"signals":[54],"may":[55],"exhibit":[56],"an":[57],"unknown":[58],"phase":[59],"relationship.":[60],"In":[61,73,136],"cases,":[63],"synchronization":[65,90,102],"needed":[67],"when":[68,115],"sending":[69],"data":[70,93,97],"across":[71],"modules.":[72],"brief,":[75],"we":[76],"present":[77],"novel":[79],"dual-clock":[81,169],"first-input-first-output":[82],"(FIFO)":[83],"buffer":[84],"that":[85],"can":[86,111,143],"handle":[87],"both":[88],"temporary":[92],"storage,":[94],"synchronizing":[96],"implicitly":[98],"through":[99],"explicit":[101],"only":[104],"flow-control":[106],"signals.":[107],"The":[108],"proposed":[109,140],"design":[110],"operate":[112],"correctly":[113],"even":[114],"transmitter":[117],"receiver":[120],"are":[121],"separated":[122],"long":[125],"link":[126,149],"whose":[127],"delay":[128],"cannot":[129],"fit":[130],"within":[131],"target":[133],"frequency.":[135],"scenarios,":[138],"FIFO":[142,171],"be":[144],"extended":[145],"to":[146,159,178],"support":[147],"multicycle":[148],"delays":[150],"in":[151],"modular":[153],"manner":[154],"with":[156,165],"minimal":[157],"modifications":[158],"baseline":[161],"architecture.":[162],"When":[163],"compared":[164],"other":[167],"state-of-the-art":[168],"designs,":[172],"new":[174],"architecture":[175],"demonstrated":[177],"yield":[179],"substantially":[181],"lower":[182],"cost":[183],"implementation.":[184]},"counts_by_year":[{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":5},{"year":2022,"cited_by_count":3},{"year":2020,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
