{"id":"https://openalex.org/W2957520949","doi":"https://doi.org/10.1109/tvlsi.2019.2924721","title":"A CMOS Majority Logic Gate and its Application to One-Step ML Decodable Codes","display_name":"A CMOS Majority Logic Gate and its Application to One-Step ML Decodable Codes","publication_year":2019,"publication_date":"2019-07-12","ids":{"openalex":"https://openalex.org/W2957520949","doi":"https://doi.org/10.1109/tvlsi.2019.2924721","mag":"2957520949"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2019.2924721","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2019.2924721","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5008575633","display_name":"Jing Guo","orcid":"https://orcid.org/0000-0002-6434-5281"},"institutions":[{"id":"https://openalex.org/I135714990","display_name":"North University of China","ror":"https://ror.org/047bp1713","country_code":"CN","type":"education","lineage":["https://openalex.org/I135714990"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Jing Guo","raw_affiliation_strings":["School of Instrument and Electronics, North University of China, Taiyuan, China"],"affiliations":[{"raw_affiliation_string":"School of Instrument and Electronics, North University of China, Taiyuan, China","institution_ids":["https://openalex.org/I135714990"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100417119","display_name":"Shanshan Liu","orcid":"https://orcid.org/0000-0001-6226-2880"},"institutions":[{"id":"https://openalex.org/I12912129","display_name":"Northeastern University","ror":"https://ror.org/04t5xt781","country_code":"US","type":"education","lineage":["https://openalex.org/I12912129"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Shanshan Liu","raw_affiliation_strings":["Department of Electronical and Computer Engineering, Northeastern University, Boston, MA, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electronical and Computer Engineering, Northeastern University, Boston, MA, USA","institution_ids":["https://openalex.org/I12912129"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100686027","display_name":"Lei Zhu","orcid":"https://orcid.org/0000-0003-2661-7052"},"institutions":[{"id":"https://openalex.org/I111971639","display_name":"Qiqihar University","ror":"https://ror.org/01khf5d59","country_code":"CN","type":"education","lineage":["https://openalex.org/I111971639"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Lei Zhu","raw_affiliation_strings":["Communication and Electronics Engineering Institute, Qiqihar University, Qiqihar, China"],"affiliations":[{"raw_affiliation_string":"Communication and Electronics Engineering Institute, Qiqihar University, Qiqihar, China","institution_ids":["https://openalex.org/I111971639"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5001979328","display_name":"Fabrizio Lombardi","orcid":"https://orcid.org/0000-0003-3152-3245"},"institutions":[{"id":"https://openalex.org/I12912129","display_name":"Northeastern University","ror":"https://ror.org/04t5xt781","country_code":"US","type":"education","lineage":["https://openalex.org/I12912129"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Fabrizio Lombardi","raw_affiliation_strings":["Department of Electronical and Computer Engineering, Northeastern University, Boston, MA, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electronical and Computer Engineering, Northeastern University, Boston, MA, USA","institution_ids":["https://openalex.org/I12912129"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5008575633"],"corresponding_institution_ids":["https://openalex.org/I135714990"],"apc_list":null,"apc_paid":null,"fwci":0.2385,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.54181442,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"27","issue":"11","first_page":"2620","last_page":"2628"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7216407060623169},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.6188139319419861},{"id":"https://openalex.org/keywords/and-or-invert","display_name":"AND-OR-Invert","score":0.600013256072998},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.517649233341217},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.49290037155151367},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4089948534965515},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.3930518925189972},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.3522796928882599},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.3132929801940918},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2879062294960022},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.21455174684524536}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7216407060623169},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.6188139319419861},{"id":"https://openalex.org/C130126468","wikidata":"https://www.wikidata.org/wiki/Q4652943","display_name":"AND-OR-Invert","level":5,"score":0.600013256072998},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.517649233341217},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.49290037155151367},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4089948534965515},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.3930518925189972},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.3522796928882599},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.3132929801940918},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2879062294960022},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21455174684524536}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2019.2924721","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2019.2924721","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G1004511159","display_name":null,"funder_award_id":"61604133","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"},{"id":"https://openalex.org/G2372245349","display_name":null,"funder_award_id":"61501275","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"}],"funders":[{"id":"https://openalex.org/F4320321001","display_name":"National Natural Science Foundation of China","ror":"https://ror.org/01h0zpd94"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W90198570","https://openalex.org/W1991087216","https://openalex.org/W2003964202","https://openalex.org/W2031113490","https://openalex.org/W2034299682","https://openalex.org/W2046773786","https://openalex.org/W2059625562","https://openalex.org/W2131862714","https://openalex.org/W2138815251","https://openalex.org/W2139608145","https://openalex.org/W2168133003","https://openalex.org/W2170328093","https://openalex.org/W2415451204","https://openalex.org/W2558003305","https://openalex.org/W2759106742","https://openalex.org/W2767653459"],"related_works":["https://openalex.org/W2789662562","https://openalex.org/W1900707063","https://openalex.org/W2098419840","https://openalex.org/W1966764473","https://openalex.org/W1977171228","https://openalex.org/W1985308002","https://openalex.org/W2542337934","https://openalex.org/W2170504327","https://openalex.org/W2121963733","https://openalex.org/W2102927888"],"abstract_inverted_index":{"The":[0,42,64,115],"majority":[1],"logic":[2],"(ML)":[3],"gate":[4],"(MLG)":[5],"is":[6,26,45,62,105,131],"required":[7],"in":[8,84,95],"fast":[9,123],"decoder":[10],"implementations":[11],"to":[12,47,121],"protect":[13],"memories":[14],"from":[15],"transient":[16],"soft":[17],"errors.":[18],"In":[19],"this":[20,146],"paper,":[21],"a":[22,31,57,70],"novel":[23],"MLG":[24],"design":[25,44,122],"proposed;":[27],"it":[28],"consists":[29],"of":[30,51,73,109,117],"pMOS":[32],"pull-up":[33],"network,":[34,38],"an":[35,40,48],"nMOS":[36],"pull-down":[37],"and":[39,87],"inverter.":[41],"proposed":[43,65,111,119,139],"applicable":[46],"arbitrary":[49],"number":[50,72],"inputs":[52],"\u03b3":[53,61],"(and":[54],"operating":[55],"as":[56,82],"mirror":[58],"circuit":[59],"when":[60,75],"odd).":[63],"designs":[66,93,112],"are":[67,113,141],"simply":[68],"requiring":[69],"small":[71],"transistors;":[74],"simulated,":[76],"they":[77],"offer":[78],"improved":[79],"metrics":[80],"such":[81],"reduction":[83],"delay,":[85],"area,":[86],"power":[88],"dissipation":[89],"compared":[90],"with":[91],"existing":[92],"found":[94],"the":[96,100,107,110,118,134,138],"technical":[97],"literature.":[98],"When":[99],"combined":[101],"power-delay-area":[102],"product":[103],"(PDAP)":[104],"considered,":[106],"advantages":[108],"pronounced.":[114],"application":[116],"MLGs":[120,140],"decoders":[124],"for":[125,145],"one-step":[126],"ML":[127],"decodable":[128],"(OS-MLD)":[129],"codes":[130],"also":[132],"presented;":[133],"results":[135],"show":[136],"that":[137],"very":[142],"efficient":[143],"circuits":[144],"coding":[147],"application.":[148]},"counts_by_year":[{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":1},{"year":2019,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}