{"id":"https://openalex.org/W2953814537","doi":"https://doi.org/10.1109/tvlsi.2019.2918768","title":"Modeling and Detectability of Full Open Gate Defects in FinFET Technology","display_name":"Modeling and Detectability of Full Open Gate Defects in FinFET Technology","publication_year":2019,"publication_date":"2019-07-07","ids":{"openalex":"https://openalex.org/W2953814537","doi":"https://doi.org/10.1109/tvlsi.2019.2918768","mag":"2953814537"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2019.2918768","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2019.2918768","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5035827251","display_name":"Freddy Forero","orcid":"https://orcid.org/0000-0001-9939-0974"},"institutions":[{"id":"https://openalex.org/I39824353","display_name":"National Institute of Astrophysics, Optics and Electronics","ror":"https://ror.org/00bpmmc63","country_code":"MX","type":"facility","lineage":["https://openalex.org/I39824353"]}],"countries":["MX"],"is_corresponding":false,"raw_author_name":"Freddy Forero","raw_affiliation_strings":["National Institute for Astrophysics, Optics and Electronics (INAOE), Puebla, M\u00e9xico"],"raw_orcid":"https://orcid.org/0000-0001-9939-0974","affiliations":[{"raw_affiliation_string":"National Institute for Astrophysics, Optics and Electronics (INAOE), Puebla, M\u00e9xico","institution_ids":["https://openalex.org/I39824353"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5006378839","display_name":"Hector Villacorta","orcid":"https://orcid.org/0000-0003-4405-4935"},"institutions":[{"id":"https://openalex.org/I86613570","display_name":"Universidad Panamericana","ror":"https://ror.org/01n1q0h77","country_code":"MX","type":"education","lineage":["https://openalex.org/I86613570"]}],"countries":["MX"],"is_corresponding":false,"raw_author_name":"Hector Villacorta","raw_affiliation_strings":["Engineering Department, Panamerica University, Aguascalientes, Mexico"],"raw_orcid":"https://orcid.org/0000-0003-4405-4935","affiliations":[{"raw_affiliation_string":"Engineering Department, Panamerica University, Aguascalientes, Mexico","institution_ids":["https://openalex.org/I86613570"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5069159925","display_name":"M. Renovell","orcid":"https://orcid.org/0000-0002-3896-8231"},"institutions":[{"id":"https://openalex.org/I4210101743","display_name":"Laboratoire d'Informatique, de Robotique et de Micro\u00e9lectronique de Montpellier","ror":"https://ror.org/013yean28","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I1326498283","https://openalex.org/I151295451","https://openalex.org/I19894307","https://openalex.org/I4210101743","https://openalex.org/I4210159245","https://openalex.org/I4405261681"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Michel Renovell","raw_affiliation_strings":["Laboratory of Informatics, Robotics and Microelectronics of Montpellier (LIRMM), Montpellier, France"],"raw_orcid":"https://orcid.org/0000-0002-3896-8231","affiliations":[{"raw_affiliation_string":"Laboratory of Informatics, Robotics and Microelectronics of Montpellier (LIRMM), Montpellier, France","institution_ids":["https://openalex.org/I4210101743"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5038219219","display_name":"Victor Champac","orcid":"https://orcid.org/0000-0002-4440-3800"},"institutions":[{"id":"https://openalex.org/I39824353","display_name":"National Institute of Astrophysics, Optics and Electronics","ror":"https://ror.org/00bpmmc63","country_code":"MX","type":"facility","lineage":["https://openalex.org/I39824353"]}],"countries":["MX"],"is_corresponding":false,"raw_author_name":"Victor Champac","raw_affiliation_strings":["National Institute for Astrophysics, Optics and Electronics (INAOE), Puebla, M\u00e9xico"],"raw_orcid":"https://orcid.org/0000-0002-4440-3800","affiliations":[{"raw_affiliation_string":"National Institute for Astrophysics, Optics and Electronics (INAOE), Puebla, M\u00e9xico","institution_ids":["https://openalex.org/I39824353"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.8476,"has_fulltext":false,"cited_by_count":15,"citation_normalized_percentile":{"value":0.74161175,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":"27","issue":"9","first_page":"2180","last_page":"2190"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.702538251876831},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6610532999038696},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.6001754999160767},{"id":"https://openalex.org/keywords/context","display_name":"Context (archaeology)","score":0.590756356716156},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5788748264312744},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5474340915679932},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.47514772415161133},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.42465782165527344},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.41893184185028076},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.3844706118106842},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3490918278694153},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3158227205276489},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.08665880560874939},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.08092418313026428},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07643488049507141}],"concepts":[{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.702538251876831},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6610532999038696},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.6001754999160767},{"id":"https://openalex.org/C2779343474","wikidata":"https://www.wikidata.org/wiki/Q3109175","display_name":"Context (archaeology)","level":2,"score":0.590756356716156},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5788748264312744},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5474340915679932},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.47514772415161133},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.42465782165527344},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.41893184185028076},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.3844706118106842},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3490918278694153},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3158227205276489},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.08665880560874939},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.08092418313026428},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07643488049507141},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/tvlsi.2019.2918768","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2019.2918768","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},{"id":"pmh:oai:HAL:lirmm-04798134v1","is_oa":false,"landing_page_url":"https://hal-lirmm.ccsd.cnrs.fr/lirmm-04798134","pdf_url":null,"source":{"id":"https://openalex.org/S4306402512","display_name":"HAL (Le Centre pour la Communication Scientifique Directe)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1294671590","host_organization_name":"Centre National de la Recherche Scientifique","host_organization_lineage":["https://openalex.org/I1294671590"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019, 27 (9), pp.2180-2190. ⟨10.1109/TVLSI.2019.2918768⟩","raw_type":"Journal articles"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.7099999785423279}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":35,"referenced_works":["https://openalex.org/W1510571840","https://openalex.org/W1584772012","https://openalex.org/W1595977007","https://openalex.org/W1966797259","https://openalex.org/W1972698239","https://openalex.org/W1988932225","https://openalex.org/W1998374178","https://openalex.org/W2029162584","https://openalex.org/W2041508134","https://openalex.org/W2049712092","https://openalex.org/W2078427776","https://openalex.org/W2094255929","https://openalex.org/W2103657905","https://openalex.org/W2104231257","https://openalex.org/W2106607114","https://openalex.org/W2117068879","https://openalex.org/W2121437951","https://openalex.org/W2122724794","https://openalex.org/W2129212061","https://openalex.org/W2134818410","https://openalex.org/W2141664222","https://openalex.org/W2143062585","https://openalex.org/W2151393930","https://openalex.org/W2153049419","https://openalex.org/W2292956491","https://openalex.org/W2568918782","https://openalex.org/W2727688201","https://openalex.org/W2751603865","https://openalex.org/W2752128027","https://openalex.org/W2771978545","https://openalex.org/W2787310733","https://openalex.org/W2800676352","https://openalex.org/W4232650785","https://openalex.org/W4237634676","https://openalex.org/W6634835962"],"related_works":["https://openalex.org/W3014521742","https://openalex.org/W2155019192","https://openalex.org/W2014709025","https://openalex.org/W2617868873","https://openalex.org/W3204141294","https://openalex.org/W4386230336","https://openalex.org/W4306968100","https://openalex.org/W2170979950","https://openalex.org/W1900707063","https://openalex.org/W2588941787"],"abstract_inverted_index":{"FinFET":[0,19,88],"technology":[1,20,83],"is":[2,12,61,149,153],"an":[3],"attractive":[4],"candidate":[5],"for":[6,15,81],"high-performance":[7],"and":[8,11,70,97,116,128,134,146,161],"power-efficient":[9],"application":[10],"currently":[13],"used":[14],"several":[16],"electronic":[17],"products.":[18],"incorporates":[21],"new":[22,31,104,123],"technologies":[23],"in":[24,78,87,140],"the":[25,45,79,121,135,138,141],"manufacturing":[26],"processes":[27],"that":[28,63,74],"may":[29],"generate":[30],"defect":[32,106,139],"topologies":[33,107],"which":[34],"need":[35],"to":[36,103],"be":[37],"considered":[38],"during":[39],"test":[40],"generation.":[41],"This":[42],"paper":[43],"analyzes":[44],"electrical":[46,118],"behavior":[47],"of":[48,120,137,143],"full":[49,110],"open":[50,68,72,111],"gate":[51,56,112],"defects,":[52],"i.e.,":[53],"a":[54],"transistor":[55],"with":[57],"infinite":[58],"resistance.":[59],"It":[60],"shown":[62],"classical":[64],"models,":[65],"called":[66,108],"single":[67],"(SO)":[69],"interconnect":[71],"(IO),":[73],"have":[75],"been":[76],"proposed":[77],"past":[80],"CMOS":[82],"are":[84,132],"not":[85],"sufficient":[86],"technology.":[89],"The":[90,114,151],"modern":[91],"FinFET-based":[92],"logic":[93],"cells":[94],"using":[95],"multifin":[96],"multifinger":[98],"design":[99],"techniques":[100],"give":[101],"rise":[102],"specific":[105],"\u201csubset":[109],"defect.\u201d":[113],"static":[115],"dynamic":[117],"behaviors":[119],"two":[122],"topologies,":[124],"subset":[125,129],"SO":[126],"(SOsub)":[127],"IO":[130],"(IOsub),":[131],"analyzed,":[133],"detectability":[136,152],"context":[142],"Boolean":[144],"testing":[145,148],"delay":[147],"derived.":[150],"analyzed":[154],"taking":[155],"into":[156],"account":[157],"process":[158],"variation,":[159],"temperature,":[160],"power":[162],"supply":[163],"control.":[164]},"counts_by_year":[{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":4},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":4},{"year":2020,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}