{"id":"https://openalex.org/W2951911020","doi":"https://doi.org/10.1109/tvlsi.2019.2918385","title":"A Novel Hybrid DRAM/STT-RAM Last-Level-Cache Architecture for Performance, Energy, and Endurance Enhancement","display_name":"A Novel Hybrid DRAM/STT-RAM Last-Level-Cache Architecture for Performance, Energy, and Endurance Enhancement","publication_year":2019,"publication_date":"2019-06-11","ids":{"openalex":"https://openalex.org/W2951911020","doi":"https://doi.org/10.1109/tvlsi.2019.2918385","mag":"2951911020"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2019.2918385","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2019.2918385","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5070038996","display_name":"Fazal Hameed","orcid":"https://orcid.org/0000-0002-2763-8755"},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"Technische Universit\u00e4t Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Fazal Hameed","raw_affiliation_strings":["Chair for Compiler Construction, Technische Universit\u00e4t Dresden, Dresden, Germany"],"raw_orcid":"https://orcid.org/0000-0002-2763-8755","affiliations":[{"raw_affiliation_string":"Chair for Compiler Construction, Technische Universit\u00e4t Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5030115692","display_name":"Jer\u00f3nimo Castrill\u00f3n","orcid":"https://orcid.org/0000-0002-5007-445X"},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"Technische Universit\u00e4t Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Jeronimo Castrillon","raw_affiliation_strings":["Chair for Compiler Construction, Technische Universit\u00e4t Dresden, Dresden, Germany"],"raw_orcid":"https://orcid.org/0000-0002-5007-445X","affiliations":[{"raw_affiliation_string":"Chair for Compiler Construction, Technische Universit\u00e4t Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I78650965"],"apc_list":null,"apc_paid":null,"fwci":0.9576,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.72804457,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"27","issue":"10","first_page":"2375","last_page":"2386"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.8720120191574097},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.6108436584472656},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6078647971153259},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5717154741287231},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5044642686843872},{"id":"https://openalex.org/keywords/random-access-memory","display_name":"Random access memory","score":0.47735142707824707},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.4464697241783142},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.4446248412132263},{"id":"https://openalex.org/keywords/non-volatile-memory","display_name":"Non-volatile memory","score":0.4221900701522827},{"id":"https://openalex.org/keywords/memory-architecture","display_name":"Memory architecture","score":0.4143977165222168},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4118898808956146},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3816767930984497},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.37215128540992737},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.22537735104560852}],"concepts":[{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.8720120191574097},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.6108436584472656},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6078647971153259},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5717154741287231},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5044642686843872},{"id":"https://openalex.org/C2994168587","wikidata":"https://www.wikidata.org/wiki/Q5295","display_name":"Random access memory","level":2,"score":0.47735142707824707},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.4464697241783142},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.4446248412132263},{"id":"https://openalex.org/C177950962","wikidata":"https://www.wikidata.org/wiki/Q10997658","display_name":"Non-volatile memory","level":2,"score":0.4221900701522827},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.4143977165222168},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4118898808956146},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3816767930984497},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.37215128540992737},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.22537735104560852},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2019.2918385","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2019.2918385","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.8899999856948853}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":36,"referenced_works":["https://openalex.org/W1968686941","https://openalex.org/W2009792503","https://openalex.org/W2036853599","https://openalex.org/W2047982556","https://openalex.org/W2048864063","https://openalex.org/W2058752853","https://openalex.org/W2064977311","https://openalex.org/W2075293780","https://openalex.org/W2082927749","https://openalex.org/W2082982763","https://openalex.org/W2084007230","https://openalex.org/W2106754364","https://openalex.org/W2112753327","https://openalex.org/W2115172404","https://openalex.org/W2125428294","https://openalex.org/W2126112620","https://openalex.org/W2128310110","https://openalex.org/W2147926533","https://openalex.org/W2148797773","https://openalex.org/W2152933730","https://openalex.org/W2187805486","https://openalex.org/W2188761345","https://openalex.org/W2310466831","https://openalex.org/W2407820757","https://openalex.org/W2613079001","https://openalex.org/W2743696392","https://openalex.org/W2763501977","https://openalex.org/W2763915470","https://openalex.org/W2793767356","https://openalex.org/W2911012662","https://openalex.org/W3142248664","https://openalex.org/W4232453610","https://openalex.org/W4285719527","https://openalex.org/W6674416589","https://openalex.org/W6678953495","https://openalex.org/W6687026183"],"related_works":["https://openalex.org/W2110995678","https://openalex.org/W2094308961","https://openalex.org/W2533585248","https://openalex.org/W4386903460","https://openalex.org/W2806599233","https://openalex.org/W2130233920","https://openalex.org/W2473808647","https://openalex.org/W4389476207","https://openalex.org/W2125880695","https://openalex.org/W2134643927"],"abstract_inverted_index":{"High-capacity":[0],"L4":[1],"architectures":[2,19],"as":[3],"a":[4,32,39,47,82,96,166],"last-level":[5],"cache":[6],"(LLC)":[7],"have":[8,20],"been":[9],"recently":[10,167],"introduced":[11],"between":[12],"L3-SRAM":[13,98],"and":[14,88,95,126,157,182,187],"off-chip":[15],"memory.":[16],"These":[17],"LLC":[18,62,93,112,119,145],"either":[21],"employed":[22],"DRAM":[23,36,175],"or":[24],"spin-transfer":[25],"torque":[26],"(STT-RAM)":[27],"memory":[28,72],"technologies.":[29],"It":[30],"is":[31,131],"known":[33],"fact":[34],"that":[35,64,101,106,143],"LLCs":[37,45],"feature":[38,46],"higher":[40],"energy":[41,181],"consumption,":[42],"while":[43,74],"STT-RAM":[44,138,152,169],"lower":[48],"write":[49],"endurance":[50,130],"compared":[51,164],"to":[52,109,165,172],"their":[53,76],"counterparts.":[54],"This":[55],"paper":[56],"proposes":[57],"an":[58,179],"efficient":[59],"hybrid":[60,92,115],"DRAM/STT-RAM":[61],"architecture":[63,116,146],"exploits":[65],"the":[66,86,91,110,118,135,148,159,173],"best":[67],"characteristics":[68],"offered":[69],"by":[70,121,133,155,162],"individual":[71],"technologies":[73],"mitigating":[75],"drawbacks.":[77],"More":[78],"precisely,":[79],"we":[80,177],"introduce":[81],"novel":[83],"mechanism":[84],"for":[85],"storage":[87],"management":[89],"of":[90,137,151,185],"tags":[94],"proactive":[97],"writeback":[99,124],"policy":[100],"combines":[102],"multiple":[103],"dirty":[104],"blocks":[105],"are":[107],"mapped":[108],"same":[111],"row.":[113],"Our":[114],"reduces":[117,147],"interference":[120],"having":[122],"less":[123],"accesses":[125],"row":[127],"fetches.":[128],"The":[129],"improved":[132],"reducing":[134],"number":[136,150],"block":[139,153],"writes.":[140],"We":[141],"show":[142],"our":[144],"total":[149],"writes":[154],"78%":[156],"improves":[158],"average":[160,180],"performance":[161,183],"13%":[163],"proposed":[168],"LLC.":[170],"Compared":[171],"state-of-the-art":[174],"LLC,":[176],"report":[178],"improvement":[184],"24%":[186],"17.1%,":[188],"respectively.":[189]},"counts_by_year":[{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2019,"cited_by_count":2}],"updated_date":"2026-03-27T05:58:40.876381","created_date":"2025-10-10T00:00:00"}
