{"id":"https://openalex.org/W2908707593","doi":"https://doi.org/10.1109/tvlsi.2018.2888958","title":"SLECTS: Slew-Driven Clock Tree Synthesis","display_name":"SLECTS: Slew-Driven Clock Tree Synthesis","publication_year":2019,"publication_date":"2019-01-10","ids":{"openalex":"https://openalex.org/W2908707593","doi":"https://doi.org/10.1109/tvlsi.2018.2888958","mag":"2908707593"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2018.2888958","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2018.2888958","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5012129149","display_name":"Weicheng Liu","orcid":"https://orcid.org/0000-0002-6561-026X"},"institutions":[{"id":"https://openalex.org/I59553526","display_name":"Stony Brook University","ror":"https://ror.org/05qghxh33","country_code":"US","type":"education","lineage":["https://openalex.org/I59553526"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Weicheng Liu","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Stony Brook University, Stony Brook, NY, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Stony Brook University, Stony Brook, NY, USA","institution_ids":["https://openalex.org/I59553526"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5033656893","display_name":"Can Sitik","orcid":"https://orcid.org/0000-0003-0056-2137"},"institutions":[{"id":"https://openalex.org/I72816309","display_name":"Drexel University","ror":"https://ror.org/04bdffz58","country_code":"US","type":"education","lineage":["https://openalex.org/I72816309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Can Sitik","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Drexel University, Philadelphia, PA, USA"],"raw_orcid":"https://orcid.org/0000-0003-0056-2137","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Drexel University, Philadelphia, PA, USA","institution_ids":["https://openalex.org/I72816309"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061262597","display_name":"Emre Salman","orcid":"https://orcid.org/0000-0001-6538-6803"},"institutions":[{"id":"https://openalex.org/I59553526","display_name":"Stony Brook University","ror":"https://ror.org/05qghxh33","country_code":"US","type":"education","lineage":["https://openalex.org/I59553526"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Emre Salman","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Stony Brook University, Stony Brook, NY, USA"],"raw_orcid":"https://orcid.org/0000-0001-6538-6803","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Stony Brook University, Stony Brook, NY, USA","institution_ids":["https://openalex.org/I59553526"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081080799","display_name":"Bar\u0131\u015f Ta\u015fk\u0131n","orcid":"https://orcid.org/0000-0002-7631-5696"},"institutions":[{"id":"https://openalex.org/I72816309","display_name":"Drexel University","ror":"https://ror.org/04bdffz58","country_code":"US","type":"education","lineage":["https://openalex.org/I72816309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Baris Taskin","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Drexel University, Philadelphia, PA, USA"],"raw_orcid":"https://orcid.org/0000-0002-7631-5696","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Drexel University, Philadelphia, PA, USA","institution_ids":["https://openalex.org/I72816309"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5063108320","display_name":"Savithri Sundareswaran","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Savithri Sundareswaran","raw_affiliation_strings":["NXP Semiconductors, Austin, TX, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"NXP Semiconductors, Austin, TX, USA","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5081113931","display_name":"Benjamin Huang","orcid":"https://orcid.org/0000-0001-9155-4890"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Benjamin Huang","raw_affiliation_strings":["NXP Semiconductors, Austin, TX, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"NXP Semiconductors, Austin, TX, USA","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.2843,"has_fulltext":false,"cited_by_count":15,"citation_normalized_percentile":{"value":0.79888241,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"27","issue":"4","first_page":"864","last_page":"874"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/timing-failure","display_name":"Timing failure","score":0.7151569128036499},{"id":"https://openalex.org/keywords/slew-rate","display_name":"Slew rate","score":0.6625621914863586},{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.6214509010314941},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.5534133911132812},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.5467877984046936},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5066643357276917},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5006899833679199},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3132629990577698},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.25494584441185},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.22607219219207764},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.21016159653663635},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.10689225792884827},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07882526516914368}],"concepts":[{"id":"https://openalex.org/C104654189","wikidata":"https://www.wikidata.org/wiki/Q7806740","display_name":"Timing failure","level":5,"score":0.7151569128036499},{"id":"https://openalex.org/C82517063","wikidata":"https://www.wikidata.org/wiki/Q1591315","display_name":"Slew rate","level":3,"score":0.6625621914863586},{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.6214509010314941},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.5534133911132812},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.5467877984046936},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5066643357276917},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5006899833679199},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3132629990577698},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.25494584441185},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.22607219219207764},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.21016159653663635},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.10689225792884827},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07882526516914368}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2018.2888958","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2018.2888958","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G3809091477","display_name":null,"funder_award_id":"2013-TJ-2450","funder_id":"https://openalex.org/F4320306087","funder_display_name":"Semiconductor Research Corporation"},{"id":"https://openalex.org/G4603192503","display_name":null,"funder_award_id":"2013-TJ-2449","funder_id":"https://openalex.org/F4320306087","funder_display_name":"Semiconductor Research Corporation"}],"funders":[{"id":"https://openalex.org/F4320306087","display_name":"Semiconductor Research Corporation","ror":"https://ror.org/047z4n946"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":30,"referenced_works":["https://openalex.org/W150248704","https://openalex.org/W601886942","https://openalex.org/W1507707340","https://openalex.org/W1963807856","https://openalex.org/W1977556410","https://openalex.org/W1984588379","https://openalex.org/W2023981464","https://openalex.org/W2024381286","https://openalex.org/W2035957933","https://openalex.org/W2056496431","https://openalex.org/W2064051475","https://openalex.org/W2115468286","https://openalex.org/W2125857172","https://openalex.org/W2128237591","https://openalex.org/W2128335981","https://openalex.org/W2133916137","https://openalex.org/W2137807823","https://openalex.org/W2142896025","https://openalex.org/W2144758504","https://openalex.org/W2146351359","https://openalex.org/W2149417654","https://openalex.org/W2164759949","https://openalex.org/W2170009145","https://openalex.org/W2170331607","https://openalex.org/W2247480952","https://openalex.org/W2326765630","https://openalex.org/W2478848959","https://openalex.org/W4230037553","https://openalex.org/W4235168608","https://openalex.org/W4250702245"],"related_works":["https://openalex.org/W2076413498","https://openalex.org/W2116259070","https://openalex.org/W2116514610","https://openalex.org/W2003180247","https://openalex.org/W2123512677","https://openalex.org/W2144282137","https://openalex.org/W2891365107","https://openalex.org/W4232019485","https://openalex.org/W4327499872","https://openalex.org/W2128528443"],"abstract_inverted_index":{"A":[0,44],"slew-driven":[1,57],"clock":[2,42,90,121,133],"tree":[3,134],"synthesis":[4,135],"(SLECTS)":[5],"methodology":[6,58],"is":[7,30,59,63,123],"proposed":[8,56],"for":[9],"nanoscale":[10],"technologies":[11],"where":[12],"the":[13,21,25,41,48,55,85,89,93],"interconnect":[14],"resistance":[15],"dominates":[16],"device":[17],"resistance,":[18],"thereby":[19],"increasing":[20],"challenge":[22],"of":[23,40,88],"satisfying":[24],"slew":[26,71,94,139],"constraint.":[27],"This":[28],"issue":[29],"exacerbated":[31],"at":[32],"lower":[33],"voltages":[34],"due":[35],"to":[36,54,68,130],"degraded":[37],"drive":[38],"ability":[39],"buffers.":[43],"paradigm":[45],"shift":[46],"from":[47],"traditional":[49],"delay":[50,80],"(and":[51],"skew)-driven":[52],"approaches":[53],"therefore":[60],"required.":[61],"SLECTS":[62],"developed":[64],"in":[65,116],"this":[66],"paper":[67],"satisfy":[69],"tight":[70],"constraints,":[72],"which":[73],"can":[74],"be":[75],"costly":[76],"or":[77],"infeasible":[78],"with":[79,110],"(skew)-driven":[81],"methodologies":[82],"and":[83,95,100,140],"reduce":[84],"power":[86,122],"dissipation":[87],"tree,":[91],"since":[92],"skew":[96,141],"constraints":[97],"are":[98],"simultaneously":[99],"methodically":[101],"considered.":[102],"Experimental":[103],"results":[104],"performed":[105],"on":[106],"an":[107],"industrial":[108],"circuit":[109],"more":[111],"than":[112],"1M":[113],"gates":[114],"designed":[115],"28-nm":[117],"technology":[118],"demonstrate":[119],"that":[120],"reduced":[124],"by":[125],"approximately":[126],"15%":[127],"as":[128],"compared":[129],"a":[131],"commercial":[132],"tool":[136],"under":[137],"similar":[138],"constraints.":[142]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
