{"id":"https://openalex.org/W2907370351","doi":"https://doi.org/10.1109/tvlsi.2018.2888625","title":"A Full Digital Fractional-&lt;inline-formula&gt; &lt;tex-math notation=\"LaTeX\"&gt;$N$ &lt;/tex-math&gt; &lt;/inline-formula&gt; TAF-FLL for Digital Applications: Demonstration of the Principle of a Frequency-Locked Loop Built on Time-Average-Frequency","display_name":"A Full Digital Fractional-&lt;inline-formula&gt; &lt;tex-math notation=\"LaTeX\"&gt;$N$ &lt;/tex-math&gt; &lt;/inline-formula&gt; TAF-FLL for Digital Applications: Demonstration of the Principle of a Frequency-Locked Loop Built on Time-Average-Frequency","publication_year":2019,"publication_date":"2019-01-04","ids":{"openalex":"https://openalex.org/W2907370351","doi":"https://doi.org/10.1109/tvlsi.2018.2888625","mag":"2907370351"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2018.2888625","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2018.2888625","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5063725597","display_name":"Liming Xiu","orcid":"https://orcid.org/0000-0003-4427-8066"},"institutions":[{"id":"https://openalex.org/I4210100976","display_name":"BOE Technology Group (China)","ror":"https://ror.org/01cwwvj38","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210100976"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Liming Xiu","raw_affiliation_strings":["BOE Technology Group Company, Ltd., Beijing, China"],"raw_orcid":"https://orcid.org/0000-0003-4427-8066","affiliations":[{"raw_affiliation_string":"BOE Technology Group Company, Ltd., Beijing, China","institution_ids":["https://openalex.org/I4210100976"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5002591607","display_name":"Xiangye Wei","orcid":"https://orcid.org/0000-0002-4252-0544"},"institutions":[{"id":"https://openalex.org/I4210100976","display_name":"BOE Technology Group (China)","ror":"https://ror.org/01cwwvj38","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210100976"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xiangye Wei","raw_affiliation_strings":["BOE Technology Group Company, Ltd., Beijing, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"BOE Technology Group Company, Ltd., Beijing, China","institution_ids":["https://openalex.org/I4210100976"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5024141610","display_name":"Yuhai Ma","orcid":"https://orcid.org/0000-0002-3449-7305"},"institutions":[{"id":"https://openalex.org/I4210100976","display_name":"BOE Technology Group (China)","ror":"https://ror.org/01cwwvj38","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210100976"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yuhai Ma","raw_affiliation_strings":["BOE Technology Group Company, Ltd., Beijing, China"],"raw_orcid":"https://orcid.org/0000-0002-3449-7305","affiliations":[{"raw_affiliation_string":"BOE Technology Group Company, Ltd., Beijing, China","institution_ids":["https://openalex.org/I4210100976"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I4210100976"],"apc_list":null,"apc_paid":null,"fwci":1.0898,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":{"value":0.773804,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":"27","issue":"3","first_page":"524","last_page":"534"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9959999918937683,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9929999709129333,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.5733457803726196},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.461870938539505},{"id":"https://openalex.org/keywords/digital-control","display_name":"Digital control","score":0.45832857489585876},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.41753771901130676},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.41392892599105835},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.3893009424209595},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.3658900260925293},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.295961856842041},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2201133370399475},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.16475516557693481}],"concepts":[{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.5733457803726196},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.461870938539505},{"id":"https://openalex.org/C158411068","wikidata":"https://www.wikidata.org/wiki/Q2720568","display_name":"Digital control","level":2,"score":0.45832857489585876},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.41753771901130676},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.41392892599105835},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.3893009424209595},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.3658900260925293},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.295961856842041},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2201133370399475},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.16475516557693481}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2018.2888625","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2018.2888625","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.49000000953674316,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":22,"referenced_works":["https://openalex.org/W9595204","https://openalex.org/W2018140995","https://openalex.org/W2021980694","https://openalex.org/W2038179376","https://openalex.org/W2059713124","https://openalex.org/W2066684071","https://openalex.org/W2084208879","https://openalex.org/W2085657659","https://openalex.org/W2107327405","https://openalex.org/W2109888209","https://openalex.org/W2110635581","https://openalex.org/W2112992788","https://openalex.org/W2118154600","https://openalex.org/W2124768176","https://openalex.org/W2132897890","https://openalex.org/W2337930151","https://openalex.org/W2485003928","https://openalex.org/W2496938897","https://openalex.org/W2611384543","https://openalex.org/W2615504945","https://openalex.org/W2792043410","https://openalex.org/W4251059014"],"related_works":["https://openalex.org/W2121182846","https://openalex.org/W1522446673","https://openalex.org/W2155789024","https://openalex.org/W2109491806","https://openalex.org/W3213608175","https://openalex.org/W2058044441","https://openalex.org/W3117675750","https://openalex.org/W2141743053","https://openalex.org/W2139484866","https://openalex.org/W2943997861"],"abstract_inverted_index":{"Time-average-frequency":[0],"(TAF)":[1],"is":[2,18,48,71,89,100,162,178],"a":[3,41,52,68,82],"novel":[4,147],"concept":[5],"proposed":[6],"in":[7,101,153],"2008":[8],"for":[9,40,157,183],"constructing":[10],"clock":[11],"signal.":[12],"TAF":[13,85,102],"direct":[14],"period":[15],"synthesis":[16,22],"(TAF-DPS)":[17],"an":[19],"emerging":[20],"frequency":[21,32,36,47,168],"technique":[23],"based":[24],"on":[25,171],"TAF.":[26,172],"Its":[27],"distinguished":[28],"features":[29,57],"are":[30,136],"small":[31],"granularity":[33],"and":[34,95,124,132,141],"fast":[35],"switching,":[37],"achieved":[38],"simultaneously":[39],"given":[42],"design.":[43],"Furthermore,":[44],"its":[45],"output":[46,99,130],"monotonically":[49],"changed":[50],"with":[51],"digital":[53,75,84,181],"control":[54,169],"word.":[55],"Those":[56],"make":[58],"it":[59,78,118],"suitable":[60],"digitally":[61],"controlled":[62],"oscillator":[63],"(DCO).":[64],"In":[65],"this":[66,176],"paper,":[67],"TAF-DPS":[69],"DCO":[70],"created":[72],"entirely":[73],"from":[74,112],"cells.":[76],"Using":[77],"as":[79],"the":[80,110,120,127,133,159,163],"core,":[81],"100%":[83],"frequency-locked":[86],"loop":[87,134,170],"(TAF-FLL)":[88],"constructed.":[90],"Unlike":[91],"all":[92],"established":[93],"FLL":[94],"PLL":[96],"architectures,":[97],"TAF-FLL's":[98],"instead":[103],"of":[104,129,138,166,175],"conventional":[105],"frequency.":[106],"This":[107,146],"fact":[108],"impacts":[109],"design":[111,135],"at":[113],"least":[114],"two":[115],"directions.":[116],"First,":[117],"blurs":[119],"boundary":[121],"between":[122],"integer-":[123],"fractional-N.":[125],"Second,":[126],"issues":[128],"jitter":[131],"independent":[137],"each":[139],"other":[140],"can":[142],"be":[143],"treated":[144],"separately.":[145],"all-digital":[148],"architecture":[149],"has":[150],"been":[151],"implemented":[152],"field-programmable":[154],"gate":[155],"array":[156],"verifying":[158],"principle.":[160],"It":[161],"first":[164],"case":[165],"building":[167],"The":[173],"purpose":[174],"TAF-FLL":[177],"to":[179],"drive":[180],"circuits,":[182],"digital-oriented":[184],"applications.":[185]},"counts_by_year":[{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":6},{"year":2020,"cited_by_count":3}],"updated_date":"2026-06-26T08:34:08.712188","created_date":"2025-10-10T00:00:00"}
