{"id":"https://openalex.org/W2907813458","doi":"https://doi.org/10.1109/tvlsi.2018.2886357","title":"Simplex FastICA: An Accelerated and Low Complex Architecture Design Methodology for $n$ D FastICA","display_name":"Simplex FastICA: An Accelerated and Low Complex Architecture Design Methodology for $n$ D FastICA","publication_year":2018,"publication_date":"2018-12-28","ids":{"openalex":"https://openalex.org/W2907813458","doi":"https://doi.org/10.1109/tvlsi.2018.2886357","mag":"2907813458"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2018.2886357","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2018.2886357","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5087944991","display_name":"Swati Bhardwaj","orcid":"https://orcid.org/0000-0001-9534-8808"},"institutions":[{"id":"https://openalex.org/I65181880","display_name":"Indian Institute of Technology Hyderabad","ror":"https://ror.org/01j4v3x97","country_code":"IN","type":"education","lineage":["https://openalex.org/I65181880"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Swati Bhardwaj","raw_affiliation_strings":["Department of Electrical Engineering, IIT Hyderabad, Hyderabad, India"],"raw_orcid":"https://orcid.org/0000-0001-9534-8808","affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, IIT Hyderabad, Hyderabad, India","institution_ids":["https://openalex.org/I65181880"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5090221410","display_name":"Shashank Raghuraman","orcid":"https://orcid.org/0000-0001-9355-0527"},"institutions":[{"id":"https://openalex.org/I65181880","display_name":"Indian Institute of Technology Hyderabad","ror":"https://ror.org/01j4v3x97","country_code":"IN","type":"education","lineage":["https://openalex.org/I65181880"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Shashank Raghuraman","raw_affiliation_strings":["Department of Electrical Engineering, IIT Hyderabad, Hyderabad, India"],"raw_orcid":"https://orcid.org/0000-0001-9355-0527","affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, IIT Hyderabad, Hyderabad, India","institution_ids":["https://openalex.org/I65181880"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5044085104","display_name":"Amit Acharyya","orcid":"https://orcid.org/0000-0002-5636-0676"},"institutions":[{"id":"https://openalex.org/I65181880","display_name":"Indian Institute of Technology Hyderabad","ror":"https://ror.org/01j4v3x97","country_code":"IN","type":"education","lineage":["https://openalex.org/I65181880"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Amit Acharyya","raw_affiliation_strings":["Department of Electrical Engineering, IIT Hyderabad, Hyderabad, India"],"raw_orcid":"https://orcid.org/0000-0002-5636-0676","affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, IIT Hyderabad, Hyderabad, India","institution_ids":["https://openalex.org/I65181880"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I65181880"],"apc_list":null,"apc_paid":null,"fwci":0.9841,"has_fulltext":false,"cited_by_count":16,"citation_normalized_percentile":{"value":0.7757047,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":93,"max":98},"biblio":{"volume":"27","issue":"5","first_page":"1124","last_page":"1137"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11447","display_name":"Blind Source Separation Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11447","display_name":"Blind Source Separation Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10320","display_name":"Neural Networks and Applications","score":0.9958000183105469,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.7183576822280884},{"id":"https://openalex.org/keywords/fastica","display_name":"FastICA","score":0.6090571880340576},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.570419192314148},{"id":"https://openalex.org/keywords/simplex","display_name":"Simplex","score":0.5450414419174194},{"id":"https://openalex.org/keywords/convergence","display_name":"Convergence (economics)","score":0.5135317444801331},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.4852147400379181},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.4707739055156708},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.42700350284576416},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3871227204799652},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3423570394515991},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.29136350750923157},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.28286176919937134},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.22479096055030823},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.21809539198875427},{"id":"https://openalex.org/keywords/channel","display_name":"Channel (broadcasting)","score":0.20627552270889282},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07444345951080322}],"concepts":[{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.7183576822280884},{"id":"https://openalex.org/C157709420","wikidata":"https://www.wikidata.org/wiki/Q3739974","display_name":"FastICA","level":4,"score":0.6090571880340576},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.570419192314148},{"id":"https://openalex.org/C62438384","wikidata":"https://www.wikidata.org/wiki/Q331350","display_name":"Simplex","level":2,"score":0.5450414419174194},{"id":"https://openalex.org/C2777303404","wikidata":"https://www.wikidata.org/wiki/Q759757","display_name":"Convergence (economics)","level":2,"score":0.5135317444801331},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.4852147400379181},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.4707739055156708},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.42700350284576416},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3871227204799652},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3423570394515991},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.29136350750923157},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.28286176919937134},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.22479096055030823},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.21809539198875427},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.20627552270889282},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07444345951080322},{"id":"https://openalex.org/C120317606","wikidata":"https://www.wikidata.org/wiki/Q17105967","display_name":"Blind signal separation","level":3,"score":0.0},{"id":"https://openalex.org/C50522688","wikidata":"https://www.wikidata.org/wiki/Q189833","display_name":"Economic growth","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/tvlsi.2018.2886357","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2018.2886357","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},{"id":"pmh:oai:raiith.iith.ac.in:4856","is_oa":false,"landing_page_url":"http://raiith.iith.ac.in/4856/","pdf_url":null,"source":{"id":"https://openalex.org/S4306400292","display_name":"Research Archive of Indian Institute of Technology Hyderabad (Indian Institute of Technology Hyderabad)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I65181880","host_organization_name":"Indian Institute of Technology Hyderabad","host_organization_lineage":["https://openalex.org/I65181880"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/8","display_name":"Decent work and economic growth","score":0.44999998807907104}],"awards":[],"funders":[{"id":"https://openalex.org/F4320310119","display_name":"Ministry of Communication and Information Technology","ror":"https://ror.org/05nmnwa45"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":43,"referenced_works":["https://openalex.org/W1480749645","https://openalex.org/W1578458555","https://openalex.org/W1633659463","https://openalex.org/W1966185057","https://openalex.org/W1971274817","https://openalex.org/W1985956780","https://openalex.org/W1994957772","https://openalex.org/W2007446032","https://openalex.org/W2010855873","https://openalex.org/W2017603933","https://openalex.org/W2019502123","https://openalex.org/W2033205888","https://openalex.org/W2060650532","https://openalex.org/W2089607228","https://openalex.org/W2099741732","https://openalex.org/W2102284731","https://openalex.org/W2108384452","https://openalex.org/W2110527401","https://openalex.org/W2115452265","https://openalex.org/W2123649031","https://openalex.org/W2124433161","https://openalex.org/W2125029645","https://openalex.org/W2130982917","https://openalex.org/W2133033960","https://openalex.org/W2133617231","https://openalex.org/W2135399108","https://openalex.org/W2139364477","https://openalex.org/W2141224535","https://openalex.org/W2141454080","https://openalex.org/W2144394309","https://openalex.org/W2145554279","https://openalex.org/W2146474141","https://openalex.org/W2149709356","https://openalex.org/W2162063828","https://openalex.org/W2162800060","https://openalex.org/W2286439238","https://openalex.org/W2293610270","https://openalex.org/W2312163514","https://openalex.org/W2409983459","https://openalex.org/W2466975593","https://openalex.org/W2570282309","https://openalex.org/W2768501499","https://openalex.org/W2769606623"],"related_works":["https://openalex.org/W2375875222","https://openalex.org/W2355600395","https://openalex.org/W2170395384","https://openalex.org/W1485204360","https://openalex.org/W2033590025","https://openalex.org/W2379345898","https://openalex.org/W2358704891","https://openalex.org/W1523023743","https://openalex.org/W2011926449","https://openalex.org/W4312121077"],"abstract_inverted_index":{"This":[0,27],"paper":[1],"proposes":[2],"an":[3,8],"n-dimensional":[4],"Simplex":[5,41],"FastICA":[6],"(FICA),":[7],"accelerated":[9],"and":[10,60,91],"low":[11],"complex":[12],"architectural":[13,52],"design":[14,165],"methodology":[15,56,140],"for":[16,24,65,102,115,123,133,162],"FICA":[17,36,42,47,104],"to":[18,121,143,152,173],"attain":[19],"high":[20],"computation":[21,99,130,159],"speed":[22],"targeted":[23],"resource-constrained":[25],"applications.":[26],"is":[28,81],"achieved":[29,136],"by":[30,62,107],"exploiting":[31],"the":[32,39,45,71,109,116,138,144,147,163,167],"algorithmic":[33],"redundancies":[34],"of":[35,111,113,129,146,158],"that":[37],"make":[38],"proposed":[40,55,139,164],"faster":[43],"than":[44],"conventional":[46],"without":[48],"adding":[49],"any":[50],"extra":[51],"complexities.":[53],"The":[54,98,126,154],"has":[57,74],"been":[58,75],"verified":[59],"validated":[61],"applying":[63],"it":[64],"separating":[66],"6D":[67],"EEG":[68],"signals.":[69],"Subsequently,":[70],"corresponding":[72],"hardware":[73],"designed":[76],"using":[77,83],"Verilog":[78],"HDL.":[79],"It":[80],"synthesized":[82],"UMC":[84],"90-nm":[85],"technology":[86],"resulting":[87],"in":[88,141],"0.5703-mW":[89],"power":[90],"0.495":[92],"mm2":[93],"area":[94],"at":[95],"1.08":[96],"V.":[97],"time":[100,131,160],"saving":[101,161],"4D-12D":[103],"was":[105],"computed":[106],"varying":[108],"number":[110],"iterations":[112],"convergence":[114],"nth":[117,134],"stage":[118,135],"from":[119,150,171],"2":[120],"4":[122],"4096":[124],"samples.":[125],"average":[127,156],"percentage":[128,157],"saved":[132],"with":[137,166],"comparison":[142],"state":[145],"art":[148],"varies":[149,170],"99.783%":[151],"99.891%.":[153],"overall":[155],"aforementioned":[168],"specifications":[169],"9.14%":[172],"16.6%.":[174]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2023,"cited_by_count":4},{"year":2022,"cited_by_count":5},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}