{"id":"https://openalex.org/W2906629987","doi":"https://doi.org/10.1109/tvlsi.2018.2884646","title":"Designing Efficient Circuits Based on Runtime-Reconfigurable Field-Effect Transistors","display_name":"Designing Efficient Circuits Based on Runtime-Reconfigurable Field-Effect Transistors","publication_year":2018,"publication_date":"2018-12-18","ids":{"openalex":"https://openalex.org/W2906629987","doi":"https://doi.org/10.1109/tvlsi.2018.2884646","mag":"2906629987"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2018.2884646","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2018.2884646","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://tud.qucosa.de/id/qucosa%3A76812","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5075349265","display_name":"Shubham Rai","orcid":"https://orcid.org/0000-0002-6522-5628"},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"Technische Universit\u00e4t Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Shubham Rai","raw_affiliation_strings":["Chair for Processor Design, Center For Advancing Electronics Dresden, Technische Universit\u00e4t Dresden, Dresden, Germany"],"affiliations":[{"raw_affiliation_string":"Chair for Processor Design, Center For Advancing Electronics Dresden, Technische Universit\u00e4t Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5003486126","display_name":"Jens Trommer","orcid":"https://orcid.org/0000-0003-2972-438X"},"institutions":[{"id":"https://openalex.org/I4210122489","display_name":"NaMLab (Germany)","ror":"https://ror.org/028070c57","country_code":"DE","type":"company","lineage":["https://openalex.org/I4210122489","https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Jens Trommer","raw_affiliation_strings":["NaMLab gGmbH, Dresden, Germany"],"affiliations":[{"raw_affiliation_string":"NaMLab gGmbH, Dresden, Germany","institution_ids":["https://openalex.org/I4210122489"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5060193481","display_name":"Michael Raitza","orcid":"https://orcid.org/0000-0003-2370-4054"},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"Technische Universit\u00e4t Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Michael Raitza","raw_affiliation_strings":["Chair for Processor Design, Center For Advancing Electronics Dresden, Technische Universit\u00e4t Dresden, Dresden, Germany"],"affiliations":[{"raw_affiliation_string":"Chair for Processor Design, Center For Advancing Electronics Dresden, Technische Universit\u00e4t Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5003850300","display_name":"Thomas Mikolajick","orcid":"https://orcid.org/0000-0003-3814-0378"},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"Technische Universit\u00e4t Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Thomas Mikolajick","raw_affiliation_strings":["IHM, Technische Universit\u00e4t Dresden, Dresden, Germany"],"affiliations":[{"raw_affiliation_string":"IHM, Technische Universit\u00e4t Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101914544","display_name":"W. Weber","orcid":"https://orcid.org/0000-0001-9504-5671"},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"Technische Universit\u00e4t Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Walter M. Weber","raw_affiliation_strings":["Center For Advancing Electronics Dresden, Technische Universit\u00e4t Dresden, Dresden, Germany"],"affiliations":[{"raw_affiliation_string":"Center For Advancing Electronics Dresden, Technische Universit\u00e4t Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100755285","display_name":"Akash Kumar","orcid":"https://orcid.org/0000-0001-7125-1737"},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"Technische Universit\u00e4t Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Akash Kumar","raw_affiliation_strings":["Chair for Processor Design, Center For Advancing Electronics Dresden, Technische Universit\u00e4t Dresden, Dresden, Germany"],"affiliations":[{"raw_affiliation_string":"Chair for Processor Design, Center For Advancing Electronics Dresden, Technische Universit\u00e4t Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5075349265"],"corresponding_institution_ids":["https://openalex.org/I78650965"],"apc_list":null,"apc_paid":null,"fwci":4.9719,"has_fulltext":false,"cited_by_count":111,"citation_normalized_percentile":{"value":0.95817802,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":99,"max":100},"biblio":{"volume":"27","issue":"3","first_page":"560","last_page":"572"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7287681102752686},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5981606841087341},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5865603089332581},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5431874990463257},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5144860744476318},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.4969647228717804},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.4920806288719177},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.4786321222782135},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.43911048769950867},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3678857088088989},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2834986746311188},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.26199495792388916},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.25068092346191406},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2494736611843109},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.06590086221694946}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7287681102752686},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5981606841087341},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5865603089332581},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5431874990463257},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5144860744476318},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.4969647228717804},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.4920806288719177},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.4786321222782135},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.43911048769950867},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3678857088088989},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2834986746311188},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.26199495792388916},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.25068092346191406},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2494736611843109},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.06590086221694946}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/tvlsi.2018.2884646","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2018.2884646","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},{"id":"pmh:oai:qucosa:de:qucosa:76812","is_oa":true,"landing_page_url":"https://tud.qucosa.de/id/qucosa%3A76812","pdf_url":null,"source":{"id":"https://openalex.org/S4377196312","display_name":"Qucosa (Saxon State and University Library Dresden)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I3132420320","host_organization_name":"SLUB Dresden","host_organization_lineage":["https://openalex.org/I3132420320"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"doc-type:Text"}],"best_oa_location":{"id":"pmh:oai:qucosa:de:qucosa:76812","is_oa":true,"landing_page_url":"https://tud.qucosa.de/id/qucosa%3A76812","pdf_url":null,"source":{"id":"https://openalex.org/S4377196312","display_name":"Qucosa (Saxon State and University Library Dresden)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I3132420320","host_organization_name":"SLUB Dresden","host_organization_lineage":["https://openalex.org/I3132420320"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"doc-type:Text"},"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G1756038278","display_name":null,"funder_award_id":"WE 4853/1-3","funder_id":"https://openalex.org/F4320320879","funder_display_name":"Deutsche Forschungsgemeinschaft"},{"id":"https://openalex.org/G6052429835","display_name":null,"funder_award_id":"(DFG)","funder_id":"https://openalex.org/F4320320879","funder_display_name":"Deutsche Forschungsgemeinschaft"}],"funders":[{"id":"https://openalex.org/F4320320879","display_name":"Deutsche Forschungsgemeinschaft","ror":"https://ror.org/018mejw64"},{"id":"https://openalex.org/F4320321613","display_name":"Technische Universit\u00e4t Dresden","ror":"https://ror.org/042aqky30"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":60,"referenced_works":["https://openalex.org/W1483713538","https://openalex.org/W1532536728","https://openalex.org/W1918485682","https://openalex.org/W1959796964","https://openalex.org/W1969849133","https://openalex.org/W1974877371","https://openalex.org/W1977426672","https://openalex.org/W1984163270","https://openalex.org/W1988747400","https://openalex.org/W1991485703","https://openalex.org/W1998516708","https://openalex.org/W2000992449","https://openalex.org/W2001346321","https://openalex.org/W2011829553","https://openalex.org/W2045823846","https://openalex.org/W2047241543","https://openalex.org/W2055215434","https://openalex.org/W2067557307","https://openalex.org/W2076349788","https://openalex.org/W2088115909","https://openalex.org/W2089442786","https://openalex.org/W2110770862","https://openalex.org/W2111832576","https://openalex.org/W2120000030","https://openalex.org/W2126596980","https://openalex.org/W2135674775","https://openalex.org/W2137858525","https://openalex.org/W2140975144","https://openalex.org/W2156694126","https://openalex.org/W2163470430","https://openalex.org/W2163492764","https://openalex.org/W2165952540","https://openalex.org/W2166127884","https://openalex.org/W2312503676","https://openalex.org/W2320443006","https://openalex.org/W2322754293","https://openalex.org/W2346682451","https://openalex.org/W2468019634","https://openalex.org/W2574807302","https://openalex.org/W2587608034","https://openalex.org/W2603052714","https://openalex.org/W2607365186","https://openalex.org/W2744604280","https://openalex.org/W2756913259","https://openalex.org/W2759368326","https://openalex.org/W2797274658","https://openalex.org/W2799027281","https://openalex.org/W2799158414","https://openalex.org/W2809707654","https://openalex.org/W2889418642","https://openalex.org/W2900265717","https://openalex.org/W4238718488","https://openalex.org/W4240435109","https://openalex.org/W4254134886","https://openalex.org/W6653525883","https://openalex.org/W6677157478","https://openalex.org/W6704780577","https://openalex.org/W6733422786","https://openalex.org/W6750289383","https://openalex.org/W6750483785"],"related_works":["https://openalex.org/W2290310756","https://openalex.org/W2170979950","https://openalex.org/W2098419840","https://openalex.org/W2526300902","https://openalex.org/W2121963733","https://openalex.org/W1985308002","https://openalex.org/W2170504327","https://openalex.org/W2542337934","https://openalex.org/W1977171228","https://openalex.org/W1990901299"],"abstract_inverted_index":{"An":[0],"early":[1],"evaluation":[2],"in":[3,10,60,118],"terms":[4],"of":[5,93,187],"circuit":[6,49,82,120,138,182],"design":[7,166],"is":[8],"essential":[9],"order":[11],"to":[12,86],"assess":[13],"the":[14,89,146,157,179,196],"feasibility":[15],"and":[16,66,113,143,184,190],"practicability":[17],"aspects":[18],"for":[19,39,72,129,167],"emerging":[20,56],"nanotechnologies.":[21,96],"Reconfigurable":[22],"nanotechnologies,":[23],"such":[24],"as":[25,36,145,154,193],"silicon":[26,174],"or":[27],"germanium":[28],"nanowire-based":[29],"reconfigurable":[30,95,110,131,176],"field-effect":[31],"transistors,":[32],"hold":[33],"great":[34],"promise":[35],"suitable":[37],"primitives":[38],"enabling":[40],"multiple":[41],"functionalities":[42],"per":[43],"computational":[44],"unit.":[45],"However,":[46],"contemporary":[47,197],"CMOS":[48,158,198],"designs":[50,83],"when":[51],"applied":[52],"directly":[53],"with":[54,156,178,195],"this":[55,98],"nanotechnology":[57],"often":[58],"result":[59],"suboptimal":[61],"designs.":[62,76,121],"For":[63],"example,":[64],"31%":[65],"71%":[67],"larger":[68],"area":[69,141],"was":[70],"obtained":[71],"our":[73],"two":[74],"exemplary":[75],"Hence,":[77],"new":[78],"approaches":[79],"delivering":[80],"tailored":[81],"are":[84],"needed":[85],"truly":[87],"tap":[88],"exciting":[90],"feature":[91],"set":[92],"these":[94,115],"To":[97],"effect,":[99],"we":[100],"propose":[101,163],"six":[102],"functionally":[103],"enhanced":[104],"logic":[105,116,171],"gates":[106,117],"based":[107],"on":[108,173],"a":[109,125,130,164,168],"nanowire":[111,175],"technology":[112],"employ":[114],"efficient":[119],"We":[122,161],"carry":[123],"out":[124],"detailed":[126],"comparative":[127],"study":[128],"multifunctional":[132],"circuit,":[133],"which":[134],"shows":[135],"better":[136],"normalized":[137,181],"delay":[139],"(20.14%),":[140],"(32.40%),":[142],"activity":[144,185],"power":[147],"metric":[148],"(40%)":[149],"while":[150],"exhibiting":[151],"similar":[152],"functionality":[153],"compared":[155,194],"reference":[159],"design.":[160],"further":[162],"novel":[165],"1-bit":[169],"arithmetic":[170],"unit-based":[172],"FETs":[177],"area,":[180],"delay,":[183],"gains":[186],"30%,":[188],"34%,":[189],"36%,":[191],"respectively,":[192],"version.":[199]},"counts_by_year":[{"year":2026,"cited_by_count":7},{"year":2025,"cited_by_count":14},{"year":2024,"cited_by_count":15},{"year":2023,"cited_by_count":25},{"year":2022,"cited_by_count":12},{"year":2021,"cited_by_count":18},{"year":2020,"cited_by_count":13},{"year":2019,"cited_by_count":7}],"updated_date":"2026-04-10T15:06:20.359241","created_date":"2025-10-10T00:00:00"}