{"id":"https://openalex.org/W2905076394","doi":"https://doi.org/10.1109/tvlsi.2018.2882567","title":"High-Volume Testing and DC Offset Trimming Technique of On-Die Bandgap Voltage Reference for SOCs and Microprocessors","display_name":"High-Volume Testing and DC Offset Trimming Technique of On-Die Bandgap Voltage Reference for SOCs and Microprocessors","publication_year":2018,"publication_date":"2018-12-12","ids":{"openalex":"https://openalex.org/W2905076394","doi":"https://doi.org/10.1109/tvlsi.2018.2882567","mag":"2905076394"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2018.2882567","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2018.2882567","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5005935863","display_name":"Takao Oshita","orcid":"https://orcid.org/0000-0001-8060-0118"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Takao Oshita","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":"https://orcid.org/0000-0001-8060-0118","affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111376807","display_name":"Jonathan Douglas","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jonathan Douglas","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5032338770","display_name":"Arun Krishnamoorthy","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Arun Krishnamoorthy","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":0.446,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.62957737,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":"27","issue":"4","first_page":"821","last_page":"829"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/trimming","display_name":"Trimming","score":0.9812451601028442},{"id":"https://openalex.org/keywords/offset","display_name":"Offset (computer science)","score":0.7222629189491272},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.6203464865684509},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5129794478416443},{"id":"https://openalex.org/keywords/bandgap-voltage-reference","display_name":"Bandgap voltage reference","score":0.4967828392982483},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.45938944816589355},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.4448852837085724},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.4341859817504883},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.33015942573547363},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.281873881816864},{"id":"https://openalex.org/keywords/voltage-reference","display_name":"Voltage reference","score":0.16563710570335388},{"id":"https://openalex.org/keywords/dropout-voltage","display_name":"Dropout voltage","score":0.09518313407897949}],"concepts":[{"id":"https://openalex.org/C56951928","wikidata":"https://www.wikidata.org/wiki/Q3539213","display_name":"Trimming","level":2,"score":0.9812451601028442},{"id":"https://openalex.org/C175291020","wikidata":"https://www.wikidata.org/wiki/Q1156822","display_name":"Offset (computer science)","level":2,"score":0.7222629189491272},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.6203464865684509},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5129794478416443},{"id":"https://openalex.org/C127033052","wikidata":"https://www.wikidata.org/wiki/Q48635","display_name":"Bandgap voltage reference","level":5,"score":0.4967828392982483},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.45938944816589355},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.4448852837085724},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.4341859817504883},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.33015942573547363},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.281873881816864},{"id":"https://openalex.org/C44351266","wikidata":"https://www.wikidata.org/wiki/Q1465532","display_name":"Voltage reference","level":3,"score":0.16563710570335388},{"id":"https://openalex.org/C15032970","wikidata":"https://www.wikidata.org/wiki/Q851210","display_name":"Dropout voltage","level":4,"score":0.09518313407897949},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2018.2882567","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2018.2882567","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W112768827","https://openalex.org/W1972039953","https://openalex.org/W2025516544","https://openalex.org/W2066369743","https://openalex.org/W2070874127","https://openalex.org/W2086328585","https://openalex.org/W2101556294","https://openalex.org/W2104609839","https://openalex.org/W2107978821","https://openalex.org/W2112611349","https://openalex.org/W2133201500","https://openalex.org/W2149539923","https://openalex.org/W2155946010","https://openalex.org/W2286199991","https://openalex.org/W2533591573","https://openalex.org/W2598706746","https://openalex.org/W4237500539","https://openalex.org/W4251449339"],"related_works":["https://openalex.org/W2467235537","https://openalex.org/W4243755427","https://openalex.org/W1493074871","https://openalex.org/W2222099502","https://openalex.org/W2128287377","https://openalex.org/W2361135282","https://openalex.org/W2057887322","https://openalex.org/W2999611009","https://openalex.org/W2947484675","https://openalex.org/W2473446198"],"abstract_inverted_index":{"Since":[0],"the":[1,11,13,16,19,31,36,46,50,62,71,74,80,85,92,100,111,117,125,132,139,155,172],"VLSI":[2,20],"chips":[3,21],"were":[4],"invented,":[5],"as":[6,168],"predicted":[7],"by":[8,131],"Moore's":[9],"law,":[10],"performance,":[12],"power,":[14],"and":[15,64,119,174],"cost":[17],"of":[18,35,91,110,113,124,147,163,171],"have":[22],"been":[23],"improved,":[24],"which":[25,97],"brought":[26],"a":[27,42,143,169],"significant":[28],"benefit":[29,44],"to":[30,49,69,73,83],"economy.":[32],"However,":[33],"some":[34],"analog":[37],"circuits":[38],"do":[39],"not":[40],"get":[41],"full":[43],"from":[45],"scaling,":[47],"due":[48],"increased":[51],"device":[52],"variability":[53],"with":[54,99,138],"transistors":[55],"in":[56],"smaller":[57],"dimension.":[58],"Under":[59],"such":[60],"circumstance,":[61],"calibration":[63],"trimming":[65,81,107,128,158,176],"techniques":[66],"are":[67],"essential":[68],"overcome":[70],"sensitivity":[72],"process":[75],"variation.":[76],"This":[77],"paper":[78],"presents":[79],"technique":[82],"correct":[84],"direct":[86],"current":[87],"(dc)":[88],"offset":[89,127,157],"error":[90],"bandgap":[93],"voltage":[94],"reference":[95],"circuit,":[96],"complies":[98,137],"high-volume":[101],"manufacturing":[102],"(HVM)":[103],"requirements.":[104,141],"The":[105,122],"proposed":[106],"method":[108,135],"consists":[109],"combination":[112],"two":[114],"different":[115],"sequences,":[116],"coarse":[118,173],"fine":[120,175],"trimming.":[121],"accuracy":[123,162],"dc":[126,156],"is":[129],"evaluated":[130],"newly":[133],"invented":[134],"that":[136],"HVM":[140],"With":[142],"compact":[144],"silicon":[145],"area":[146],"only":[148],"700":[149],"\u03bcm":[150],"<sup":[151],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[152],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[153],",":[154],"circuit":[159],"achieved":[160],"an":[161],"\u00b15":[164],"mV":[165],"(4\u03c3":[166],")":[167],"result":[170],"operations.":[177]},"counts_by_year":[{"year":2026,"cited_by_count":2},{"year":2025,"cited_by_count":2},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":3}],"updated_date":"2026-06-26T08:34:08.712188","created_date":"2025-10-10T00:00:00"}