{"id":"https://openalex.org/W2900440653","doi":"https://doi.org/10.1109/tvlsi.2018.2876917","title":"A Simulation-Based Metric to Guide Glitch Power Reduction in Digital Circuits","display_name":"A Simulation-Based Metric to Guide Glitch Power Reduction in Digital Circuits","publication_year":2018,"publication_date":"2018-11-08","ids":{"openalex":"https://openalex.org/W2900440653","doi":"https://doi.org/10.1109/tvlsi.2018.2876917","mag":"2900440653"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2018.2876917","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2018.2876917","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5087170806","display_name":"Shivani Bathla","orcid":"https://orcid.org/0000-0002-1109-0836"},"institutions":[{"id":"https://openalex.org/I24676775","display_name":"Indian Institute of Technology Madras","ror":"https://ror.org/03v0r5n49","country_code":"IN","type":"facility","lineage":["https://openalex.org/I24676775"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Shivani Bathla","raw_affiliation_strings":["Department of Electrical Engineering, IIT Madras, Chennai, India"],"raw_orcid":"https://orcid.org/0000-0002-1109-0836","affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, IIT Madras, Chennai, India","institution_ids":["https://openalex.org/I24676775"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103068738","display_name":"Rahul Rao","orcid":"https://orcid.org/0000-0002-7784-7029"},"institutions":[{"id":"https://openalex.org/I4210129961","display_name":"IBM (India)","ror":"https://ror.org/034ahpr11","country_code":"IN","type":"company","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210129961"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Rahul M. Rao","raw_affiliation_strings":["IBM India Pvt. Ltd., Bengaluru, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IBM India Pvt. Ltd., Bengaluru, India","institution_ids":["https://openalex.org/I4210129961"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5009851991","display_name":"Nitin Chandrachoodan","orcid":"https://orcid.org/0000-0002-9258-7317"},"institutions":[{"id":"https://openalex.org/I24676775","display_name":"Indian Institute of Technology Madras","ror":"https://ror.org/03v0r5n49","country_code":"IN","type":"facility","lineage":["https://openalex.org/I24676775"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Nitin Chandrachoodan","raw_affiliation_strings":["Department of Electrical Engineering, IIT Madras, Chennai, India"],"raw_orcid":"https://orcid.org/0000-0002-9258-7317","affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, IIT Madras, Chennai, India","institution_ids":["https://openalex.org/I24676775"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5087170806"],"corresponding_institution_ids":["https://openalex.org/I24676775"],"apc_list":null,"apc_paid":null,"fwci":0.2627,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":{"value":0.54592661,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":"27","issue":"2","first_page":"376","last_page":"386"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/glitch","display_name":"Glitch","score":0.9765130281448364},{"id":"https://openalex.org/keywords/metric","display_name":"Metric (unit)","score":0.8050259351730347},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.7050204277038574},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6586759090423584},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.5744436979293823},{"id":"https://openalex.org/keywords/spurious-relationship","display_name":"Spurious relationship","score":0.5394890904426575},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.5168002843856812},{"id":"https://openalex.org/keywords/convergence","display_name":"Convergence (economics)","score":0.4920463263988495},{"id":"https://openalex.org/keywords/minification","display_name":"Minification","score":0.4718133211135864},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.42120304703712463},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.40299975872039795},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.40244901180267334},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.39865195751190186},{"id":"https://openalex.org/keywords/real-time-computing","display_name":"Real-time computing","score":0.328334242105484},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.22154980897903442},{"id":"https://openalex.org/keywords/detector","display_name":"Detector","score":0.15731260180473328},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1529501974582672},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.09495499730110168}],"concepts":[{"id":"https://openalex.org/C191287063","wikidata":"https://www.wikidata.org/wiki/Q543281","display_name":"Glitch","level":3,"score":0.9765130281448364},{"id":"https://openalex.org/C176217482","wikidata":"https://www.wikidata.org/wiki/Q860554","display_name":"Metric (unit)","level":2,"score":0.8050259351730347},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.7050204277038574},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6586759090423584},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.5744436979293823},{"id":"https://openalex.org/C97256817","wikidata":"https://www.wikidata.org/wiki/Q1462316","display_name":"Spurious relationship","level":2,"score":0.5394890904426575},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.5168002843856812},{"id":"https://openalex.org/C2777303404","wikidata":"https://www.wikidata.org/wiki/Q759757","display_name":"Convergence (economics)","level":2,"score":0.4920463263988495},{"id":"https://openalex.org/C147764199","wikidata":"https://www.wikidata.org/wiki/Q6865248","display_name":"Minification","level":2,"score":0.4718133211135864},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.42120304703712463},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.40299975872039795},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.40244901180267334},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.39865195751190186},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.328334242105484},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.22154980897903442},{"id":"https://openalex.org/C94915269","wikidata":"https://www.wikidata.org/wiki/Q1834857","display_name":"Detector","level":2,"score":0.15731260180473328},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1529501974582672},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.09495499730110168},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C50522688","wikidata":"https://www.wikidata.org/wiki/Q189833","display_name":"Economic growth","level":1,"score":0.0},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2018.2876917","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2018.2876917","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320307762","display_name":"International Business Machines Corporation","ror":"https://ror.org/05hh8d621"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W1992619037","https://openalex.org/W2021452258","https://openalex.org/W2096424065","https://openalex.org/W2115028095","https://openalex.org/W2118014020","https://openalex.org/W2128215251","https://openalex.org/W2128264388","https://openalex.org/W2133762912","https://openalex.org/W2133784609","https://openalex.org/W2135804390","https://openalex.org/W2158151684","https://openalex.org/W2161828911","https://openalex.org/W2534813697","https://openalex.org/W3149866969","https://openalex.org/W4249832276","https://openalex.org/W6679240198","https://openalex.org/W6679982624","https://openalex.org/W6680190179","https://openalex.org/W6684652846"],"related_works":["https://openalex.org/W2067166883","https://openalex.org/W2161481161","https://openalex.org/W1995923616","https://openalex.org/W1597557306","https://openalex.org/W2900440653","https://openalex.org/W1958405720","https://openalex.org/W2991418621","https://openalex.org/W2115102698","https://openalex.org/W1595418108","https://openalex.org/W4206210640"],"abstract_inverted_index":{"In":[0],"this":[1,99],"paper,":[2],"we":[3,30],"propose":[4],"an":[5],"algorithm":[6,122],"to":[7,35,45,91,106],"classify":[8],"spurious":[9],"transitions":[10],"in":[11,63,127],"the":[12,27,37,47,103,108,117],"activity":[13],"of":[14,74,110],"a":[15,32,67,85],"digital":[16],"circuit":[17],"as":[18],"generated":[19],"and":[20,115],"propagated":[21],"glitches":[22],"during":[23],"logic":[24,130],"simulation.":[25],"Using":[26],"activities":[28],"obtained,":[29],"compute":[31],"criticality":[33],"metric":[34,52,105],"identify":[36],"nets":[38],"where":[39],"glitch":[40,64,75,81,95,112],"minimization":[41],"techniques":[42,57,114],"are":[43,58],"likely":[44],"provide":[46],"maximum":[48],"benefit.":[49],"The":[50,120],"proposed":[51,104,121],"provides":[53],"insight":[54],"into":[55],"which":[56],"best":[59],"suited":[60],"for":[61,66],"use":[62],"reduction":[65,76,113],"given":[68],"circuit.":[69],"This":[70],"enables":[71],"targeted":[72],"application":[73,109],"techniques.":[77],"Experiments":[78],"with":[79,93],"several":[80],"intensive":[82],"benchmarks":[83],"show":[84],"faster":[86],"convergence":[87],"within":[88],"fewer":[89],"iterations":[90],"solutions":[92],"reduced":[94],"activity.":[96],"We":[97],"validate":[98],"observation":[100],"by":[101],"using":[102],"guide":[107],"some":[111],"quantify":[116],"resultant":[118],"savings.":[119],"can":[123],"be":[124],"seamlessly":[125],"incorporated":[126],"modern":[128],"event-driven":[129],"simulators.":[131]},"counts_by_year":[{"year":2025,"cited_by_count":4},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":2},{"year":2020,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
