{"id":"https://openalex.org/W2890915229","doi":"https://doi.org/10.1109/tvlsi.2018.2864316","title":"Automated Phase-Noise-Aware Design of RF Clock Distribution Circuits","display_name":"Automated Phase-Noise-Aware Design of RF Clock Distribution Circuits","publication_year":2018,"publication_date":"2018-09-04","ids":{"openalex":"https://openalex.org/W2890915229","doi":"https://doi.org/10.1109/tvlsi.2018.2864316","mag":"2890915229"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2018.2864316","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2018.2864316","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5083016917","display_name":"Dimo Martev","orcid":"https://orcid.org/0000-0002-7347-865X"},"institutions":[{"id":"https://openalex.org/I62916508","display_name":"Technical University of Munich","ror":"https://ror.org/02kkvpp62","country_code":"DE","type":"education","lineage":["https://openalex.org/I62916508"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Dimo Martev","raw_affiliation_strings":["Chair of Electronic Design Automation, Technical University of Munich, Munich, Germany"],"raw_orcid":"https://orcid.org/0000-0002-7347-865X","affiliations":[{"raw_affiliation_string":"Chair of Electronic Design Automation, Technical University of Munich, Munich, Germany","institution_ids":["https://openalex.org/I62916508"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5000995844","display_name":"Sven Hampel","orcid":"https://orcid.org/0000-0001-8958-0977"},"institutions":[{"id":"https://openalex.org/I3166620746","display_name":"Sennheiser (Germany)","ror":"https://ror.org/02gwwga82","country_code":"DE","type":"company","lineage":["https://openalex.org/I3166620746"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Sven Hampel","raw_affiliation_strings":["Sennheiser electronic GmbH&Co KG, Wedemark, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Sennheiser electronic GmbH&Co KG, Wedemark, Germany","institution_ids":["https://openalex.org/I3166620746"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5017567485","display_name":"Ulf Schlichtmann","orcid":"https://orcid.org/0000-0003-4431-7619"},"institutions":[{"id":"https://openalex.org/I62916508","display_name":"Technical University of Munich","ror":"https://ror.org/02kkvpp62","country_code":"DE","type":"education","lineage":["https://openalex.org/I62916508"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Ulf Schlichtmann","raw_affiliation_strings":["Chair of Electronic Design Automation, Technical University of Munich, Munich, Germany"],"raw_orcid":"https://orcid.org/0000-0003-4431-7619","affiliations":[{"raw_affiliation_string":"Chair of Electronic Design Automation, Technical University of Munich, Munich, Germany","institution_ids":["https://openalex.org/I62916508"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5083016917"],"corresponding_institution_ids":["https://openalex.org/I62916508"],"apc_list":null,"apc_paid":null,"fwci":0.3927,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.63821017,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":95},"biblio":{"volume":"26","issue":"11","first_page":"2395","last_page":"2405"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/netlist","display_name":"Netlist","score":0.7665000557899475},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6231681704521179},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5568966269493103},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.5275539755821228},{"id":"https://openalex.org/keywords/toolchain","display_name":"Toolchain","score":0.5272803902626038},{"id":"https://openalex.org/keywords/noise","display_name":"Noise (video)","score":0.5110758543014526},{"id":"https://openalex.org/keywords/phase-noise","display_name":"Phase noise","score":0.48150548338890076},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.46085184812545776},{"id":"https://openalex.org/keywords/sizing","display_name":"Sizing","score":0.4513886272907257},{"id":"https://openalex.org/keywords/floorplan","display_name":"Floorplan","score":0.43765005469322205},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.4272664785385132},{"id":"https://openalex.org/keywords/spice","display_name":"Spice","score":0.42238202691078186},{"id":"https://openalex.org/keywords/place-and-route","display_name":"Place and route","score":0.41594380140304565},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.41361522674560547},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.35666215419769287},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.27284717559814453},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.23418116569519043},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.20679107308387756},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.16289111971855164}],"concepts":[{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.7665000557899475},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6231681704521179},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5568966269493103},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.5275539755821228},{"id":"https://openalex.org/C2777062904","wikidata":"https://www.wikidata.org/wiki/Q545406","display_name":"Toolchain","level":3,"score":0.5272803902626038},{"id":"https://openalex.org/C99498987","wikidata":"https://www.wikidata.org/wiki/Q2210247","display_name":"Noise (video)","level":3,"score":0.5110758543014526},{"id":"https://openalex.org/C89631360","wikidata":"https://www.wikidata.org/wiki/Q1428766","display_name":"Phase noise","level":2,"score":0.48150548338890076},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.46085184812545776},{"id":"https://openalex.org/C2777767291","wikidata":"https://www.wikidata.org/wiki/Q1080291","display_name":"Sizing","level":2,"score":0.4513886272907257},{"id":"https://openalex.org/C130145326","wikidata":"https://www.wikidata.org/wiki/Q1553985","display_name":"Floorplan","level":2,"score":0.43765005469322205},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.4272664785385132},{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.42238202691078186},{"id":"https://openalex.org/C127879752","wikidata":"https://www.wikidata.org/wiki/Q3390760","display_name":"Place and route","level":3,"score":0.41594380140304565},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.41361522674560547},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.35666215419769287},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.27284717559814453},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.23418116569519043},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.20679107308387756},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.16289111971855164},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.0},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2018.2864316","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2018.2864316","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6100000143051147,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320307102","display_name":"Intel Corporation","ror":"https://ror.org/01ek73717"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W1497256448","https://openalex.org/W1550474463","https://openalex.org/W1564201208","https://openalex.org/W1569550779","https://openalex.org/W2052586721","https://openalex.org/W2065577281","https://openalex.org/W2084792706","https://openalex.org/W2097388262","https://openalex.org/W2097749440","https://openalex.org/W2108324407","https://openalex.org/W2130675388","https://openalex.org/W2135250302","https://openalex.org/W2143022706","https://openalex.org/W2160252016","https://openalex.org/W2614501763","https://openalex.org/W2757948977","https://openalex.org/W3147616483","https://openalex.org/W4237162529","https://openalex.org/W4242244648","https://openalex.org/W6634336121"],"related_works":["https://openalex.org/W2350308400","https://openalex.org/W3091557894","https://openalex.org/W1962246972","https://openalex.org/W2060497355","https://openalex.org/W1995821058","https://openalex.org/W2030503305","https://openalex.org/W4386859294","https://openalex.org/W4292829262","https://openalex.org/W2089341644","https://openalex.org/W4380987687"],"abstract_inverted_index":{"This":[0],"paper":[1,180],"presents":[2],"a":[3,18,25,35,48,154],"methodology":[4,14,97,141],"for":[5,27,43,112,161],"phase-noise-aware":[6],"design":[7,140,144,183],"of":[8,24,90,127,146,173,185],"RF":[9,147,186],"clock":[10,148,187],"distribution":[11,149,188],"networks.":[12,189],"The":[13,61,93,118,138],"is":[15,177],"embedded":[16],"within":[17,107],"commercial":[19,132],"digital":[20],"toolchain.":[21],"It":[22,105],"consists":[23],"method":[26,69],"phase":[28,62],"noise":[29,59,63],"analysis":[30],"based":[31],"on":[32,70,181],"lookup":[33],"tables,":[34],"buffer":[36,95],"insertion":[37,96],"algorithm":[38,51],"providing":[39],"an":[40],"optimal":[41],"buffering":[42],"large":[44,102],"interconnect":[45],"trees":[46],"and":[47,167],"gate":[49,119],"sizing":[50,120],"that":[52],"offers":[53,122],"fast":[54],"power":[55],"minimization,":[56],"subject":[57],"to":[58,87,110,124,131,153],"constraints.":[60],"estimate":[64],"produced":[65],"by":[66,73,157],"the":[67,143,159,171,178,182],"proposed":[68,94,139],"average":[71],"deviates":[72],"less":[74],"than":[75],"3.45%":[76],"from":[77,151],"SPICE":[78],"simulation":[79],"results;":[80],"however,":[81],"it":[82],"can":[83,98],"be":[84],"computed":[85],"three":[86,123],"five":[88],"orders":[89,126],"magnitude":[91,128],"faster.":[92],"easily":[99],"handle":[100],"very":[101],"industrial":[103],"examples.":[104],"completes":[106],"seconds,":[108],"compared":[109,130],"days":[111],"methodologies":[113],"used":[114],"in":[115],"industry":[116],"today.":[117],"optimization":[121],"four":[125],"speedup,":[129],"products,":[133],"while":[134],"producing":[135],"comparable":[136],"results.":[137],"reduces":[142],"time":[145],"networks":[150],"weeks":[152],"few":[155],"hours":[156],"eliminating":[158],"need":[160],"manual":[162,168],"circuit":[163],"design,":[164],"analog":[165],"simulations,":[166],"layout.":[169],"To":[170],"extent":[172],"our":[174],"knowledge,":[175],"this":[176],"first":[179],"automation":[184]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2018,"cited_by_count":1}],"updated_date":"2026-03-27T05:58:40.876381","created_date":"2025-10-10T00:00:00"}