{"id":"https://openalex.org/W2894441261","doi":"https://doi.org/10.1109/tvlsi.2018.2856527","title":"A Repair-for-Diagnosis Methodology for Logic Circuits","display_name":"A Repair-for-Diagnosis Methodology for Logic Circuits","publication_year":2018,"publication_date":"2018-07-31","ids":{"openalex":"https://openalex.org/W2894441261","doi":"https://doi.org/10.1109/tvlsi.2018.2856527","mag":"2894441261"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2018.2856527","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2018.2856527","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5103259979","display_name":"Cheng-Hung Wu","orcid":"https://orcid.org/0000-0002-0475-5756"},"institutions":[{"id":"https://openalex.org/I91807558","display_name":"National Cheng Kung University","ror":"https://ror.org/01b8kcc49","country_code":"TW","type":"education","lineage":["https://openalex.org/I91807558"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Cheng-Hung Wu","raw_affiliation_strings":["Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan"],"raw_orcid":"https://orcid.org/0000-0002-0475-5756","affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan","institution_ids":["https://openalex.org/I91807558"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5017790235","display_name":"Sheng-Lin Lin","orcid":"https://orcid.org/0000-0002-8546-954X"},"institutions":[{"id":"https://openalex.org/I901624438","display_name":"Realtek (Taiwan)","ror":"https://ror.org/05x1ffr83","country_code":"TW","type":"company","lineage":["https://openalex.org/I901624438"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Sheng-Lin Lin","raw_affiliation_strings":["RealTek Semiconductor Corporation, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"RealTek Semiconductor Corporation, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I901624438"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5079657769","display_name":"Kuen-Jong Lee","orcid":"https://orcid.org/0000-0002-6690-0074"},"institutions":[{"id":"https://openalex.org/I91807558","display_name":"National Cheng Kung University","ror":"https://ror.org/01b8kcc49","country_code":"TW","type":"education","lineage":["https://openalex.org/I91807558"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Kuen-Jong Lee","raw_affiliation_strings":["Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan"],"raw_orcid":"https://orcid.org/0000-0002-6690-0074","affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan","institution_ids":["https://openalex.org/I91807558"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5077101123","display_name":"S.M. Reddy","orcid":"https://orcid.org/0000-0001-9208-8262"},"institutions":[{"id":"https://openalex.org/I126307644","display_name":"University of Iowa","ror":"https://ror.org/036jqmy94","country_code":"US","type":"education","lineage":["https://openalex.org/I126307644"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sudhakar M. Reddy","raw_affiliation_strings":["Department of Electrical and Computer Engineering, The University of Iowa, Iowa City, IA, USA"],"raw_orcid":"https://orcid.org/0000-0001-9208-8262","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, The University of Iowa, Iowa City, IA, USA","institution_ids":["https://openalex.org/I126307644"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.9502,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.76107522,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":"26","issue":"11","first_page":"2254","last_page":"2267"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.7279154062271118},{"id":"https://openalex.org/keywords/limiting","display_name":"Limiting","score":0.6954620480537415},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5862445831298828},{"id":"https://openalex.org/keywords/fault","display_name":"Fault (geology)","score":0.574774980545044},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.5482726693153381},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5418238639831543},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5104852914810181},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.4923938512802124},{"id":"https://openalex.org/keywords/yield","display_name":"Yield (engineering)","score":0.47378775477409363},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4230336546897888},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.41592830419540405},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.4125310778617859},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.16754400730133057},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.10220471024513245},{"id":"https://openalex.org/keywords/mechanical-engineering","display_name":"Mechanical engineering","score":0.08421400189399719}],"concepts":[{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.7279154062271118},{"id":"https://openalex.org/C188198153","wikidata":"https://www.wikidata.org/wiki/Q1613840","display_name":"Limiting","level":2,"score":0.6954620480537415},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5862445831298828},{"id":"https://openalex.org/C175551986","wikidata":"https://www.wikidata.org/wiki/Q47089","display_name":"Fault (geology)","level":2,"score":0.574774980545044},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.5482726693153381},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5418238639831543},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5104852914810181},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.4923938512802124},{"id":"https://openalex.org/C134121241","wikidata":"https://www.wikidata.org/wiki/Q899301","display_name":"Yield (engineering)","level":2,"score":0.47378775477409363},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4230336546897888},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.41592830419540405},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.4125310778617859},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.16754400730133057},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.10220471024513245},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.08421400189399719},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C165205528","wikidata":"https://www.wikidata.org/wiki/Q83371","display_name":"Seismology","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C191897082","wikidata":"https://www.wikidata.org/wiki/Q11467","display_name":"Metallurgy","level":1,"score":0.0},{"id":"https://openalex.org/C127313418","wikidata":"https://www.wikidata.org/wiki/Q1069","display_name":"Geology","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2018.2856527","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2018.2856527","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G3205872255","display_name":null,"funder_award_id":"NSC102-2221-E-006-266-MY3","funder_id":"https://openalex.org/F4320321040","funder_display_name":"National Science Council"}],"funders":[{"id":"https://openalex.org/F4320321040","display_name":"National Science Council","ror":"https://ror.org/02kv4zf79"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":45,"referenced_works":["https://openalex.org/W1554885925","https://openalex.org/W1812126616","https://openalex.org/W1849928240","https://openalex.org/W1973423723","https://openalex.org/W1975922194","https://openalex.org/W2007796286","https://openalex.org/W2014091871","https://openalex.org/W2022412407","https://openalex.org/W2033806113","https://openalex.org/W2055589924","https://openalex.org/W2059003023","https://openalex.org/W2065847128","https://openalex.org/W2080147108","https://openalex.org/W2086926157","https://openalex.org/W2089128866","https://openalex.org/W2092357065","https://openalex.org/W2096146619","https://openalex.org/W2108914014","https://openalex.org/W2112375479","https://openalex.org/W2112559786","https://openalex.org/W2115005577","https://openalex.org/W2120412521","https://openalex.org/W2129954472","https://openalex.org/W2131814033","https://openalex.org/W2132584944","https://openalex.org/W2133454107","https://openalex.org/W2143846508","https://openalex.org/W2170254026","https://openalex.org/W2170290165","https://openalex.org/W2186922790","https://openalex.org/W2187831645","https://openalex.org/W2343549777","https://openalex.org/W2345901286","https://openalex.org/W2414280258","https://openalex.org/W2562269381","https://openalex.org/W2567901352","https://openalex.org/W2612483706","https://openalex.org/W2787570284","https://openalex.org/W3117267865","https://openalex.org/W4302458519","https://openalex.org/W6672822051","https://openalex.org/W6681228468","https://openalex.org/W6685062322","https://openalex.org/W6705108459","https://openalex.org/W6787428562"],"related_works":["https://openalex.org/W2378211422","https://openalex.org/W2745001401","https://openalex.org/W4321353415","https://openalex.org/W2130974462","https://openalex.org/W972276598","https://openalex.org/W4246352526","https://openalex.org/W2028665553","https://openalex.org/W4230315250","https://openalex.org/W2086519370","https://openalex.org/W2087343574"],"abstract_inverted_index":{"Fault":[0],"diagnosis":[1,60],"plays":[2],"a":[3,101,147,159,168],"major":[4],"role":[5],"in":[6,18,109,167,193],"IC":[7],"yield":[8,15,46,95,122,185],"enhancement":[9],"as":[10,83],"it":[11,163],"can":[12,136,206],"help":[13],"identify":[14],"limiting":[16,87,96,123,186],"defects":[17,25,187],"fabricated":[19],"devices.":[20],"The":[21,143],"information":[22],"on":[23,221],"such":[24],"is":[26],"used":[27],"to":[28,31,36,51,93,104,112,161,174,234],"guide":[29],"modifications":[30],"design":[32,195,212],"and/or":[33,59],"fabrication":[34],"processes":[35],"improve":[37,113,235],"yield.":[38],"These":[39],"steps":[40],"may":[41],"be":[42,131,137,207],"iterated":[43],"until":[44],"acceptable":[45],"levels":[47],"are":[48,80,181,188,199],"achieved.":[49],"Due":[50],"circuit":[52,148],"structure":[53],"and":[54,68,79,90,116,190,196,223],"limitations":[55],"of":[56,66,121,158,170,204,230],"the":[57,64,119,140,177,184,194,201,210,228,231],"tests":[58,67,135],"procedures":[61],"used,":[62],"after":[63],"application":[65],"logic":[69,110,154,203],"diagnosis,":[70],"many":[71],"detectable":[72],"faults":[73,128,166],"remain":[74],"undistinguished":[75,106,171],"from":[76,164,209],"each":[77],"other":[78,165],"reported":[81],"out":[82],"suspected":[84],"defects,":[85],"thus":[86],"diagnostic":[88,114,236],"resolution":[89,115],"affecting":[91],"ability":[92],"pinpoint":[94],"defects.":[97,124],"This":[98],"paper":[99],"proposes":[100],"repair-for-diagnosis":[102,205],"method":[103,144,233],"distinguish":[105,162],"fault":[107,160],"pairs":[108],"circuits":[111,226],"hence":[117],"facilitate":[118],"determination":[120],"Even":[125],"functionally":[126],"equivalent":[127],"which":[129],"cannot":[130],"distinguished":[132,138],"by":[133,151],"any":[134],"using":[139],"proposed":[141,145,178,232],"method.":[142],"augments":[146],"under":[149],"consideration":[150],"adding":[152],"redundant":[153],"that":[155],"allows":[156],"repair":[157,179],"group":[169],"faults.":[172],"Procedures":[173],"efficiently":[175],"use":[176],"strategy":[180],"given.":[182],"Once":[183],"identified":[189],"corrective":[191],"actions":[192],"manufacturing":[197],"process":[198],"done,":[200],"additional":[202],"deleted":[208],"final":[211],"for":[213],"volume":[214],"production":[215],"with":[216],"desired":[217],"yields.":[218],"Experimental":[219],"results":[220],"ISCAS-89":[222],"IWLS05":[224],"benchmark":[225],"demonstrate":[227],"efficacy":[229],"resolution.":[237]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2020,"cited_by_count":3},{"year":2018,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
