{"id":"https://openalex.org/W2807689278","doi":"https://doi.org/10.1109/tvlsi.2018.2838044","title":"A Fast, Single-Instruction\u2013Multiple-Data, Scalable Priority Queue","display_name":"A Fast, Single-Instruction\u2013Multiple-Data, Scalable Priority Queue","publication_year":2018,"publication_date":"2018-06-07","ids":{"openalex":"https://openalex.org/W2807689278","doi":"https://doi.org/10.1109/tvlsi.2018.2838044","mag":"2807689278"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2018.2838044","is_oa":true,"landing_page_url":"https://doi.org/10.1109/tvlsi.2018.2838044","pdf_url":"https://ieeexplore.ieee.org/ielx7/92/8472222/08374984.pdf","source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"bronze","oa_url":"https://ieeexplore.ieee.org/ielx7/92/8472222/08374984.pdf","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5055594983","display_name":"Imad Benacer","orcid":"https://orcid.org/0000-0001-9608-2474"},"institutions":[{"id":"https://openalex.org/I45683168","display_name":"Polytechnique Montr\u00e9al","ror":"https://ror.org/05f8d4e86","country_code":"CA","type":"education","lineage":["https://openalex.org/I45683168"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Imad Benacer","raw_affiliation_strings":["Department of Computer and Software Engineering, \u00c9cole Polytechnique de Montr\u00e9al, Montr\u00e9al, QC, Canada"],"raw_orcid":"https://orcid.org/0000-0001-9608-2474","affiliations":[{"raw_affiliation_string":"Department of Computer and Software Engineering, \u00c9cole Polytechnique de Montr\u00e9al, Montr\u00e9al, QC, Canada","institution_ids":["https://openalex.org/I45683168"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111748115","display_name":"Fran\u00e7ois-Raymond Boyer","orcid":null},"institutions":[{"id":"https://openalex.org/I45683168","display_name":"Polytechnique Montr\u00e9al","ror":"https://ror.org/05f8d4e86","country_code":"CA","type":"education","lineage":["https://openalex.org/I45683168"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Francois-Raymond Boyer","raw_affiliation_strings":["Department of Computer and Software Engineering, \u00c9cole Polytechnique de Montr\u00e9al, Montr\u00e9al, QC, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer and Software Engineering, \u00c9cole Polytechnique de Montr\u00e9al, Montr\u00e9al, QC, Canada","institution_ids":["https://openalex.org/I45683168"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5038488044","display_name":"Yvon Savaria","orcid":"https://orcid.org/0000-0002-3404-9959"},"institutions":[{"id":"https://openalex.org/I45683168","display_name":"Polytechnique Montr\u00e9al","ror":"https://ror.org/05f8d4e86","country_code":"CA","type":"education","lineage":["https://openalex.org/I45683168"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Yvon Savaria","raw_affiliation_strings":["Department of Electrical Engineering, \u00c9cole Polytechnique de Montr\u00e9al, Montr\u00e9al, QC, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, \u00c9cole Polytechnique de Montr\u00e9al, Montr\u00e9al, QC, Canada","institution_ids":["https://openalex.org/I45683168"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I45683168"],"apc_list":null,"apc_paid":null,"fwci":1.0287,"has_fulltext":true,"cited_by_count":7,"citation_normalized_percentile":{"value":0.80322151,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"26","issue":"10","first_page":"1939","last_page":"1952"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10772","display_name":"Distributed systems and fault tolerance","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10772","display_name":"Distributed systems and fault tolerance","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10138","display_name":"Network Traffic and Congestion Control","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7554910182952881},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.6324489116668701},{"id":"https://openalex.org/keywords/priority-queue","display_name":"Priority queue","score":0.5306270122528076},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5265296697616577},{"id":"https://openalex.org/keywords/queue","display_name":"Queue","score":0.4986410140991211},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.24966081976890564},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.10504928231239319}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7554910182952881},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.6324489116668701},{"id":"https://openalex.org/C26951474","wikidata":"https://www.wikidata.org/wiki/Q629283","display_name":"Priority queue","level":3,"score":0.5306270122528076},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5265296697616577},{"id":"https://openalex.org/C160403385","wikidata":"https://www.wikidata.org/wiki/Q220543","display_name":"Queue","level":2,"score":0.4986410140991211},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.24966081976890564},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.10504928231239319}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/tvlsi.2018.2838044","is_oa":true,"landing_page_url":"https://doi.org/10.1109/tvlsi.2018.2838044","pdf_url":"https://ieeexplore.ieee.org/ielx7/92/8472222/08374984.pdf","source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},{"id":"pmh:oai:publications.polymtl.ca:41474","is_oa":false,"landing_page_url":"https://publications.polymtl.ca/41474/","pdf_url":null,"source":{"id":"https://openalex.org/S4306401013","display_name":"PolyPublie (\u00c9cole Polytechnique de Montr\u00e9al)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I45683168","host_organization_name":"Polytechnique Montr\u00e9al","host_organization_lineage":["https://openalex.org/I45683168"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Article de revue"}],"best_oa_location":{"id":"doi:10.1109/tvlsi.2018.2838044","is_oa":true,"landing_page_url":"https://doi.org/10.1109/tvlsi.2018.2838044","pdf_url":"https://ieeexplore.ieee.org/ielx7/92/8472222/08374984.pdf","source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"sustainable_development_goals":[{"score":0.4099999964237213,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320334593","display_name":"Natural Sciences and Engineering Research Council of Canada","ror":"https://ror.org/01h531d29"}],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2807689278.pdf","grobid_xml":"https://content.openalex.org/works/W2807689278.grobid-xml"},"referenced_works_count":35,"referenced_works":["https://openalex.org/W1512417440","https://openalex.org/W1971597759","https://openalex.org/W1974962040","https://openalex.org/W1975746772","https://openalex.org/W1978233821","https://openalex.org/W2011444829","https://openalex.org/W2041300124","https://openalex.org/W2045749024","https://openalex.org/W2049042771","https://openalex.org/W2055232798","https://openalex.org/W2055676969","https://openalex.org/W2065483852","https://openalex.org/W2096819083","https://openalex.org/W2115264714","https://openalex.org/W2116134748","https://openalex.org/W2119733805","https://openalex.org/W2124067630","https://openalex.org/W2132996124","https://openalex.org/W2134488935","https://openalex.org/W2137239103","https://openalex.org/W2145251822","https://openalex.org/W2150348132","https://openalex.org/W2169660606","https://openalex.org/W2172250608","https://openalex.org/W2182091276","https://openalex.org/W2463379156","https://openalex.org/W2487583538","https://openalex.org/W2548294119","https://openalex.org/W2744118842","https://openalex.org/W2752061190","https://openalex.org/W2752853835","https://openalex.org/W2963634393","https://openalex.org/W4231339499","https://openalex.org/W6677906779","https://openalex.org/W6744529318"],"related_works":["https://openalex.org/W2748952813","https://openalex.org/W2036343335","https://openalex.org/W2384565571","https://openalex.org/W189328514","https://openalex.org/W2262651858","https://openalex.org/W2951223296","https://openalex.org/W4297169359","https://openalex.org/W2143289692","https://openalex.org/W1974858599","https://openalex.org/W3049636605"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"we":[3,87],"address":[4],"a":[5,21,41,63,71,89,115,158],"key":[6,18],"challenge":[7],"in":[8,40,66,73,100,114,138],"designing":[9],"flow-based":[10],"traffic":[11,67],"managers":[12],"(TMs)":[13],"for":[14,49,171],"next-generation":[15],"networks.":[16],"One":[17],"functionality":[19],"of":[20,28,76,109,121,123,167],"TM":[22,53],"is":[23,62,70,130,136,143],"to":[24,96,145,186],"schedule":[25],"the":[26,45,74,105,124,152,165,168],"departure":[27],"packets":[29,37,99],"on":[30,157],"egress":[31],"ports.":[32],"This":[33,155],"scheduling":[34],"ensures":[35],"that":[36,43],"are":[38],"sent":[39],"way":[42],"meets":[44],"allowed":[46],"bandwidth":[47],"quotas":[48],"each":[50],"flow.":[51],"A":[52,119],"handles":[54],"policing,":[55],"shaping,":[56],"scheduling,":[57],"and":[58,69,84,112,189],"queuing.":[59],"The":[60,132],"latter":[61],"core":[64],"function":[65],"management":[68],"bottleneck":[72],"context":[75],"high-speed":[77],"network":[78],"devices.":[79],"Aiming":[80],"at":[81,194],"high":[82],"throughput":[83],"low":[85],"latency,":[86],"propose":[88],"single-instruction-multiple-data":[90],"(SIMD)":[91],"hardware":[92,126],"priority":[93],"queue":[94,173],"(PQ)":[95],"sort":[97],"out":[98],"real":[101],"time,":[102],"supporting":[103],"independently":[104],"three":[106],"basic":[107],"operations":[108],"enqueuing,":[110],"dequeuing,":[111],"replacing":[113],"single":[116],"clock":[117],"cycle.":[118],"proof":[120],"validity":[122],"proposed":[125,169],"PQ":[127,134],"data":[128],"structure":[129],"presented.":[131],"implemented":[133],"architecture":[135],"coded":[137],"C++.":[139],"Vivado":[140],"high-level":[141],"synthesis":[142],"used":[144],"generate":[146],"synthesizable":[147],"register":[148],"transfer":[149],"logic":[150],"from":[151],"C++":[153],"model.":[154],"implementation":[156],"ZC706":[159],"field-programmable":[160],"gate":[161],"array":[162],"(FPGA)":[163],"shows":[164],"scalability":[166],"solution":[170],"various":[172],"depths":[174],"with":[175],"almost":[176],"constant":[177],"performance.":[178],"It":[179],"offers":[180],"a$10\\times":[181],"$throughput":[182],"improvement":[183],"when":[184],"compared":[185],"prior":[187],"works,":[188],"it":[190],"supports":[191],"links":[192],"operating":[193],"100":[195],"Gb/s.":[196]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":2}],"updated_date":"2026-07-29T09:40:50.615796","created_date":"2025-10-10T00:00:00"}