{"id":"https://openalex.org/W2806282611","doi":"https://doi.org/10.1109/tvlsi.2018.2837681","title":"DCMCS: Highly Robust Low-Power Differential Current-Mode Clocking and Synthesis","display_name":"DCMCS: Highly Robust Low-Power Differential Current-Mode Clocking and Synthesis","publication_year":2018,"publication_date":"2018-05-31","ids":{"openalex":"https://openalex.org/W2806282611","doi":"https://doi.org/10.1109/tvlsi.2018.2837681","mag":"2806282611"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2018.2837681","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2018.2837681","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5072825788","display_name":"Riadul Islam","orcid":"https://orcid.org/0000-0002-4649-3467"},"institutions":[{"id":"https://openalex.org/I4210130704","display_name":"University of Michigan\u2013Dearborn","ror":"https://ror.org/035wtm547","country_code":"US","type":"education","lineage":["https://openalex.org/I4210130704"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Riadul Islam","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Michigan at Dearborn, Dearborn, MI, USA"],"raw_orcid":"https://orcid.org/0000-0002-4649-3467","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Michigan at Dearborn, Dearborn, MI, USA","institution_ids":["https://openalex.org/I4210130704"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5042765713","display_name":"Hany Fahmy","orcid":null},"institutions":[{"id":"https://openalex.org/I185103710","display_name":"University of California, Santa Cruz","ror":"https://ror.org/03s65by71","country_code":"US","type":"education","lineage":["https://openalex.org/I185103710"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Hany A. Fahmy","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of California at Santa Cruz, Santa Cruz, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of California at Santa Cruz, Santa Cruz, CA, USA","institution_ids":["https://openalex.org/I185103710"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101037010","display_name":"Ping Y. Lin","orcid":null},"institutions":[{"id":"https://openalex.org/I185103710","display_name":"University of California, Santa Cruz","ror":"https://ror.org/03s65by71","country_code":"US","type":"education","lineage":["https://openalex.org/I185103710"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ping Y. Lin","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of California at Santa Cruz, Santa Cruz, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of California at Santa Cruz, Santa Cruz, CA, USA","institution_ids":["https://openalex.org/I185103710"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5065218759","display_name":"Matthew R. Guthaus","orcid":"https://orcid.org/0000-0002-8113-4531"},"institutions":[{"id":"https://openalex.org/I185103710","display_name":"University of California, Santa Cruz","ror":"https://ror.org/03s65by71","country_code":"US","type":"education","lineage":["https://openalex.org/I185103710"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Matthew R. Guthaus","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of California at Santa Cruz, Santa Cruz, CA, USA"],"raw_orcid":"https://orcid.org/0000-0002-8113-4531","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of California at Santa Cruz, Santa Cruz, CA, USA","institution_ids":["https://openalex.org/I185103710"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":{"value":2645,"currency":"USD","value_usd":2645},"apc_paid":null,"fwci":0.2072,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.54035377,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":"26","issue":"10","first_page":"2108","last_page":"2117"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9976000189781189,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9965999722480774,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.7379056811332703},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.6787670850753784},{"id":"https://openalex.org/keywords/current-mode-logic","display_name":"Current-mode logic","score":0.6679369211196899},{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.6464715003967285},{"id":"https://openalex.org/keywords/robustness","display_name":"Robustness (evolution)","score":0.6456699371337891},{"id":"https://openalex.org/keywords/cpu-multiplier","display_name":"CPU multiplier","score":0.626148521900177},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6015832424163818},{"id":"https://openalex.org/keywords/clock-network","display_name":"Clock network","score":0.5354934334754944},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4838065505027771},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.48301610350608826},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.4748944342136383},{"id":"https://openalex.org/keywords/low-power-electronics","display_name":"Low-power electronics","score":0.449440062046051},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.43014946579933167},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.4249914884567261},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.4195806086063385},{"id":"https://openalex.org/keywords/power-analysis","display_name":"Power analysis","score":0.4146340489387512},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.3611990511417389},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.2408066987991333},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.21834483742713928},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.21312037110328674},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.17870154976844788},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.11685401201248169}],"concepts":[{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.7379056811332703},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.6787670850753784},{"id":"https://openalex.org/C2780295579","wikidata":"https://www.wikidata.org/wiki/Q5195108","display_name":"Current-mode logic","level":3,"score":0.6679369211196899},{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.6464715003967285},{"id":"https://openalex.org/C63479239","wikidata":"https://www.wikidata.org/wiki/Q7353546","display_name":"Robustness (evolution)","level":3,"score":0.6456699371337891},{"id":"https://openalex.org/C125576049","wikidata":"https://www.wikidata.org/wiki/Q2246273","display_name":"CPU multiplier","level":5,"score":0.626148521900177},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6015832424163818},{"id":"https://openalex.org/C2778182565","wikidata":"https://www.wikidata.org/wiki/Q1752879","display_name":"Clock network","level":5,"score":0.5354934334754944},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4838065505027771},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.48301610350608826},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.4748944342136383},{"id":"https://openalex.org/C117551214","wikidata":"https://www.wikidata.org/wiki/Q6692774","display_name":"Low-power electronics","level":4,"score":0.449440062046051},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.43014946579933167},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.4249914884567261},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.4195806086063385},{"id":"https://openalex.org/C71743495","wikidata":"https://www.wikidata.org/wiki/Q2845210","display_name":"Power analysis","level":3,"score":0.4146340489387512},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.3611990511417389},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.2408066987991333},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21834483742713928},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.21312037110328674},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.17870154976844788},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.11685401201248169},{"id":"https://openalex.org/C104317684","wikidata":"https://www.wikidata.org/wiki/Q7187","display_name":"Gene","level":2,"score":0.0},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0}],"mesh":[],"locations_count":5,"locations":[{"id":"doi:10.1109/tvlsi.2018.2837681","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2018.2837681","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},{"id":"pmh:oai:escholarship.org/ark:/13030/qt2hh0p6d0","is_oa":false,"landing_page_url":"https://escholarship.org/uc/item/2hh0p6d0","pdf_url":null,"source":{"id":"https://openalex.org/S4306400115","display_name":"eScholarship (California Digital Library)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I2801248553","host_organization_name":"California Digital Library","host_organization_lineage":["https://openalex.org/I2801248553"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, vol 26, iss 10","raw_type":"article"},{"id":"pmh:oai:escholarship.org/ark:/13030/qt7jg6x9dg","is_oa":false,"landing_page_url":"https://escholarship.org/uc/item/7jg6x9dg","pdf_url":null,"source":{"id":"https://openalex.org/S4306400115","display_name":"eScholarship (California Digital Library)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I2801248553","host_organization_name":"California Digital Library","host_organization_lineage":["https://openalex.org/I2801248553"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION SYSTEMS, vol 26, iss 10","raw_type":"article"},{"id":"pmh:qt2hh0p6d0","is_oa":false,"landing_page_url":"http://www.escholarship.org/uc/item/2hh0p6d0","pdf_url":null,"source":{"id":"https://openalex.org/S4306400115","display_name":"eScholarship (California Digital Library)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I2801248553","host_organization_name":"California Digital Library","host_organization_lineage":["https://openalex.org/I2801248553"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Islam, R; Fahmy, HA; Lin, PY; &amp; Guthaus, MR. (2018). DCMCS: Highly Robust Low-Power Differential Current-Mode Clocking and Synthesis. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 26(10), 2108 - 2117. doi: 10.1109/TVLSI.2018.2837681. UC Santa Cruz: Retrieved from: http://www.escholarship.org/uc/item/2hh0p6d0","raw_type":"article"},{"id":"pmh:qt7jg6x9dg","is_oa":false,"landing_page_url":"http://www.escholarship.org/uc/item/7jg6x9dg","pdf_url":null,"source":{"id":"https://openalex.org/S4306400115","display_name":"eScholarship (California Digital Library)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I2801248553","host_organization_name":"California Digital Library","host_organization_lineage":["https://openalex.org/I2801248553"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Islam, Riadul; Fahmy, Hany A.; Lin, Ping Y.; &amp; Guthaus, Matthew R.(2018). DCMCS: Highly Robust Low-Power DifferentialCurrent-Mode Clocking and Synthesis. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION SYSTEMS, 26(10). UC Santa Cruz: Retrieved from: http://www.escholarship.org/uc/item/7jg6x9dg","raw_type":"article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.7900000214576721}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":34,"referenced_works":["https://openalex.org/W1535610321","https://openalex.org/W1547369456","https://openalex.org/W1606989584","https://openalex.org/W1745769330","https://openalex.org/W1776668917","https://openalex.org/W1905341465","https://openalex.org/W1972190598","https://openalex.org/W1974610062","https://openalex.org/W2012162936","https://openalex.org/W2013867895","https://openalex.org/W2035551293","https://openalex.org/W2041950850","https://openalex.org/W2086159412","https://openalex.org/W2102765057","https://openalex.org/W2122435992","https://openalex.org/W2127074586","https://openalex.org/W2128433628","https://openalex.org/W2129797382","https://openalex.org/W2137585364","https://openalex.org/W2143808685","https://openalex.org/W2146568502","https://openalex.org/W2148342678","https://openalex.org/W2148609278","https://openalex.org/W2152789742","https://openalex.org/W2154778518","https://openalex.org/W2158130267","https://openalex.org/W2161283733","https://openalex.org/W2162708751","https://openalex.org/W2518702004","https://openalex.org/W2742696816","https://openalex.org/W4232271862","https://openalex.org/W4237096326","https://openalex.org/W4249768725","https://openalex.org/W7055689883"],"related_works":["https://openalex.org/W2474747038","https://openalex.org/W2559451387","https://openalex.org/W2088914741","https://openalex.org/W4247180033","https://openalex.org/W2137310043","https://openalex.org/W1978275142","https://openalex.org/W2337711143","https://openalex.org/W4313332229","https://openalex.org/W3006003651","https://openalex.org/W1508592555"],"abstract_inverted_index":{"In":[0,71],"this":[1],"paper,":[2],"we":[3,73],"present":[4],"a":[5,17,29,36,47,92],"new":[6],"differential":[7,53],"current-mode":[8,66],"pulsed":[9],"flip-flop":[10],"(DCMPFF)":[11],"for":[12],"low-power":[13],"clock":[14,50,68,89,111],"distribution":[15],"using":[16],"representative":[18],"45-nm":[19],"CMOS":[20],"technology.":[21],"Experimental":[22],"results":[23],"show":[24],"that":[25],"the":[26,42,52,75,85,114],"DCMPFF":[27,43],"has":[28],"47%":[30],"faster":[31],"clock-to-output":[32],"(CLK-Q)":[33],"delay":[34],"than":[35],"traditional":[37],"voltagemode":[38],"(VM)-pulsed":[39],"FF.":[40],"When":[41],"is":[44,117],"integrated":[45],"with":[46,105],"DCM":[48,77,115],"H-tree":[49],"distribution,":[51],"technique":[54],"saves":[55,99],"53%":[56],"and":[57,64,79,87,101,107,122],"26%":[58],"power":[59,90,104],"compared":[60],"to":[61,83,119],"conventional":[62],"VM":[63],"previous":[65],"(CM)":[67],"networks,":[69],"respectively.":[70,126],"addition,":[72],"propose":[74],"first":[76],"clocking":[78,98],"synthesis":[80],"(DCMCS)":[81],"methodology":[82],"improve":[84],"robustness":[86],"overall":[88],"of":[91],"network.":[93],"The":[94],"proposed":[95],"DCMCS-based":[96],"electromigrationaware":[97],"79%":[100],"51%":[102],"average":[103],"7.7":[106],"11.3":[108],"ps":[109],"lower":[110],"skew":[112],"when":[113],"scheme":[116],"applied":[118],"ISPD":[120],"2009":[121],"2010":[123],"test":[124],"benches,":[125]},"counts_by_year":[{"year":2025,"cited_by_count":4},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2018,"cited_by_count":2}],"updated_date":"2026-08-31T07:19:18.363097","created_date":"2025-10-10T00:00:00"}
