{"id":"https://openalex.org/W2802875048","doi":"https://doi.org/10.1109/tvlsi.2018.2826440","title":"Multilevel Half-Rate Phase Detector for Clock and Data Recovery Circuits","display_name":"Multilevel Half-Rate Phase Detector for Clock and Data Recovery Circuits","publication_year":2018,"publication_date":"2018-04-23","ids":{"openalex":"https://openalex.org/W2802875048","doi":"https://doi.org/10.1109/tvlsi.2018.2826440","mag":"2802875048"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2018.2826440","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2018.2826440","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"http://hdl.handle.net/2078.1/199147","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5020334235","display_name":"C. Gimeno","orcid":"https://orcid.org/0000-0003-4261-7837"},"institutions":[{"id":"https://openalex.org/I95674353","display_name":"UCLouvain","ror":"https://ror.org/02495e989","country_code":"BE","type":"education","lineage":["https://openalex.org/I95674353"]}],"countries":["BE"],"is_corresponding":false,"raw_author_name":"Cecilia Gimeno","raw_affiliation_strings":["ICTEAM Institute, Universit\u00e9 catholique de Louvain, Louvain\u2013La-Neuve, Belgium"],"raw_orcid":"https://orcid.org/0000-0003-4261-7837","affiliations":[{"raw_affiliation_string":"ICTEAM Institute, Universit\u00e9 catholique de Louvain, Louvain\u2013La-Neuve, Belgium","institution_ids":["https://openalex.org/I95674353"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5065138463","display_name":"David Bol","orcid":"https://orcid.org/0000-0002-2678-1613"},"institutions":[{"id":"https://openalex.org/I95674353","display_name":"UCLouvain","ror":"https://ror.org/02495e989","country_code":"BE","type":"education","lineage":["https://openalex.org/I95674353"]}],"countries":["BE"],"is_corresponding":false,"raw_author_name":"David Bol","raw_affiliation_strings":["ICTEAM Institute, Universit\u00e9 catholique de Louvain, Louvain\u2013La-Neuve, Belgium"],"raw_orcid":"https://orcid.org/0000-0002-2678-1613","affiliations":[{"raw_affiliation_string":"ICTEAM Institute, Universit\u00e9 catholique de Louvain, Louvain\u2013La-Neuve, Belgium","institution_ids":["https://openalex.org/I95674353"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5064026729","display_name":"Denis Flandre","orcid":"https://orcid.org/0000-0001-5298-5196"},"institutions":[{"id":"https://openalex.org/I95674353","display_name":"UCLouvain","ror":"https://ror.org/02495e989","country_code":"BE","type":"education","lineage":["https://openalex.org/I95674353"]}],"countries":["BE"],"is_corresponding":false,"raw_author_name":"Denis Flandre","raw_affiliation_strings":["ICTEAM Institute, Universit\u00e9 catholique de Louvain, Louvain\u2013La-Neuve, Belgium"],"raw_orcid":"https://orcid.org/0000-0001-5298-5196","affiliations":[{"raw_affiliation_string":"ICTEAM Institute, Universit\u00e9 catholique de Louvain, Louvain\u2013La-Neuve, Belgium","institution_ids":["https://openalex.org/I95674353"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I95674353"],"apc_list":{"value":2645,"currency":"USD","value_usd":2645},"apc_paid":null,"fwci":0.3998,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.60744931,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"26","issue":"9","first_page":"1807","last_page":"1811"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9937999844551086,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10299","display_name":"Photonic and Optical Devices","score":0.9905999898910522,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.8164933919906616},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.7302346229553223},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6655402779579163},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5880717635154724},{"id":"https://openalex.org/keywords/phase-detector","display_name":"Phase detector","score":0.5779480934143066},{"id":"https://openalex.org/keywords/phase-frequency-detector","display_name":"Phase frequency detector","score":0.4859798848628998},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.48226672410964966},{"id":"https://openalex.org/keywords/voltage-controlled-oscillator","display_name":"Voltage-controlled oscillator","score":0.4720538258552551},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4522831439971924},{"id":"https://openalex.org/keywords/detector","display_name":"Detector","score":0.4458160400390625},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.39997345209121704},{"id":"https://openalex.org/keywords/charge-pump","display_name":"Charge pump","score":0.3778887987136841},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.35204559564590454},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.30236876010894775},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.25774282217025757},{"id":"https://openalex.org/keywords/capacitor","display_name":"Capacitor","score":0.17485013604164124}],"concepts":[{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.8164933919906616},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.7302346229553223},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6655402779579163},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5880717635154724},{"id":"https://openalex.org/C110086884","wikidata":"https://www.wikidata.org/wiki/Q2085341","display_name":"Phase detector","level":3,"score":0.5779480934143066},{"id":"https://openalex.org/C2776158855","wikidata":"https://www.wikidata.org/wiki/Q2085341","display_name":"Phase frequency detector","level":5,"score":0.4859798848628998},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.48226672410964966},{"id":"https://openalex.org/C5291336","wikidata":"https://www.wikidata.org/wiki/Q852341","display_name":"Voltage-controlled oscillator","level":3,"score":0.4720538258552551},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4522831439971924},{"id":"https://openalex.org/C94915269","wikidata":"https://www.wikidata.org/wiki/Q1834857","display_name":"Detector","level":2,"score":0.4458160400390625},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.39997345209121704},{"id":"https://openalex.org/C114825011","wikidata":"https://www.wikidata.org/wiki/Q440704","display_name":"Charge pump","level":4,"score":0.3778887987136841},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.35204559564590454},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.30236876010894775},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.25774282217025757},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.17485013604164124}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/tvlsi.2018.2826440","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2018.2826440","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},{"id":"pmh:oai:dial.uclouvain.be:boreal:199147","is_oa":true,"landing_page_url":"http://hdl.handle.net/2078.1/199147","pdf_url":null,"source":{"id":"https://openalex.org/S4306401902","display_name":"Digital Access to Libraries (Universit\u00e9 catholique de Louvain (UCL), l'Universit\u00e9 de Namur (UNamur) and the Universit\u00e9 Saint-Louis (USL-B))","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I95674353","host_organization_name":"UCLouvain","host_organization_lineage":["https://openalex.org/I95674353"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems, , p. 5 (2018)","raw_type":"info:eu-repo/semantics/article"}],"best_oa_location":{"id":"pmh:oai:dial.uclouvain.be:boreal:199147","is_oa":true,"landing_page_url":"http://hdl.handle.net/2078.1/199147","pdf_url":null,"source":{"id":"https://openalex.org/S4306401902","display_name":"Digital Access to Libraries (Universit\u00e9 catholique de Louvain (UCL), l'Universit\u00e9 de Namur (UNamur) and the Universit\u00e9 Saint-Louis (USL-B))","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I95674353","host_organization_name":"UCLouvain","host_organization_lineage":["https://openalex.org/I95674353"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems, , p. 5 (2018)","raw_type":"info:eu-repo/semantics/article"},"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.8299999833106995,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320321390","display_name":"Fonds De La Recherche Scientifique - FNRS","ror":"https://ror.org/03q83t159"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1970492126","https://openalex.org/W1992579604","https://openalex.org/W2003473732","https://openalex.org/W2051152465","https://openalex.org/W2123892792","https://openalex.org/W2123943867","https://openalex.org/W2125398712","https://openalex.org/W2132897890","https://openalex.org/W2163697349","https://openalex.org/W2172802475","https://openalex.org/W2508073187","https://openalex.org/W2524390067","https://openalex.org/W2580924773","https://openalex.org/W6663509128"],"related_works":["https://openalex.org/W2369807905","https://openalex.org/W2089131288","https://openalex.org/W4385624389","https://openalex.org/W2979324006","https://openalex.org/W4381745543","https://openalex.org/W1600405202","https://openalex.org/W2908219865","https://openalex.org/W2087564251","https://openalex.org/W2558244976","https://openalex.org/W3177439118"],"abstract_inverted_index":{"In":[0],"this":[1],"brief,":[2],"a":[3,55,85,106,116,129,152],"half-rate":[4],"(HR)":[5],"bang-bang":[6],"(BB)":[7],"phase":[8,47],"detector":[9],"(PD)":[10],"with":[11,84,128,148],"multiple":[12],"decision":[13],"levels":[14],"is":[15],"proposed":[16,111,143],"for":[17,162],"clock":[18,81],"and":[19,43],"data":[20,35],"recovery":[21],"(CDR)":[22],"circuits.":[23],"The":[24,110],"combination":[25],"allows":[26,54],"the":[27,33,41,46,50,59,62,65,70,94,156,169],"oscillator":[28,63],"to":[29,77,92,103,159],"run":[30],"at":[31],"half":[32],"input":[34],"rate":[36,97],"while":[37],"providing":[38,121],"information":[39],"about":[40],"sign":[42],"magnitude":[44],"of":[45,58,61,69,132,155],"shift":[48],"between":[49],"PD":[51,157],"inputs.":[52],"This":[53,166],"liner":[56],"control":[57],"frequency":[60],"in":[64,75,105,115,144],"phase-locked":[66],"loop":[67],"(PLL)":[68],"CDR":[71,108,147],"circuit,":[72],"which":[73],"results":[74],"up":[76,102],"30%":[78],"less":[79],"output":[80],"jitter":[82],"than":[83],"conventional":[86],"two-levels":[87],"HR":[88,164],"BB":[89,138],"PD.":[90],"Thanks":[91],"this,":[93],"bit":[95],"error":[96],"can":[98],"be":[99,160],"decreased":[100],"by":[101],"5\u00d7":[104],"5-Gb/s":[107],"circuit.":[109],"topology":[112],"was":[113],"implemented":[114,161],"28-nm":[117],"FDSOI":[118],"CMOS":[119],"technology":[120],"average":[122],"power":[123],"consumption":[124],"below":[125],"76":[126],"\u03bcW":[127],"supply":[130],"voltage":[131],"1":[133],"V.":[134],"Although":[135],"multilevel":[136],"(ML)":[137],"PDs":[139],"have":[140],"already":[141],"been":[142],"some":[145],"PLL-based":[146],"very":[149],"interesting":[150],"results,":[151],"specific":[153],"design":[154],"has":[158],"an":[163],"system.":[165],"brief":[167],"provides":[168],"first":[170],"ML-HR-BBPD.":[171]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":1}],"updated_date":"2026-08-21T09:56:20.448147","created_date":"2025-10-10T00:00:00"}