{"id":"https://openalex.org/W2795915628","doi":"https://doi.org/10.1109/tvlsi.2018.2815603","title":"Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA","display_name":"Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA","publication_year":2018,"publication_date":"2018-04-03","ids":{"openalex":"https://openalex.org/W2795915628","doi":"https://doi.org/10.1109/tvlsi.2018.2815603","mag":"2795915628"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2018.2815603","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2018.2815603","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5068840674","display_name":"Yufei Ma","orcid":"https://orcid.org/0000-0002-2670-524X"},"institutions":[{"id":"https://openalex.org/I55732556","display_name":"Arizona State University","ror":"https://ror.org/03efmqc40","country_code":"US","type":"education","lineage":["https://openalex.org/I55732556"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yufei Ma","raw_affiliation_strings":["School of Electrical, Computer, and Energy Engineering, Arizona State University, Tempe, AZ, USA"],"raw_orcid":"https://orcid.org/0000-0002-2670-524X","affiliations":[{"raw_affiliation_string":"School of Electrical, Computer, and Energy Engineering, Arizona State University, Tempe, AZ, USA","institution_ids":["https://openalex.org/I55732556"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100740019","display_name":"Yu Cao","orcid":"https://orcid.org/0000-0001-6968-1180"},"institutions":[{"id":"https://openalex.org/I55732556","display_name":"Arizona State University","ror":"https://ror.org/03efmqc40","country_code":"US","type":"education","lineage":["https://openalex.org/I55732556"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yu Cao","raw_affiliation_strings":["School of Electrical, Computer, and Energy Engineering, Arizona State University, Tempe, AZ, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical, Computer, and Energy Engineering, Arizona State University, Tempe, AZ, USA","institution_ids":["https://openalex.org/I55732556"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5030130819","display_name":"Sarma Vrudhula","orcid":"https://orcid.org/0000-0001-9278-2959"},"institutions":[{"id":"https://openalex.org/I55732556","display_name":"Arizona State University","ror":"https://ror.org/03efmqc40","country_code":"US","type":"education","lineage":["https://openalex.org/I55732556"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sarma Vrudhula","raw_affiliation_strings":["School of Computing, Informatics, Decision Systems Engineering, Arizona State University, Tempe, AZ, USA"],"raw_orcid":"https://orcid.org/0000-0001-9278-2959","affiliations":[{"raw_affiliation_string":"School of Computing, Informatics, Decision Systems Engineering, Arizona State University, Tempe, AZ, USA","institution_ids":["https://openalex.org/I55732556"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5007690955","display_name":"Jae-sun Seo","orcid":"https://orcid.org/0000-0002-4551-7789"},"institutions":[{"id":"https://openalex.org/I55732556","display_name":"Arizona State University","ror":"https://ror.org/03efmqc40","country_code":"US","type":"education","lineage":["https://openalex.org/I55732556"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jae-sun Seo","raw_affiliation_strings":["School of Electrical, Computer, and Energy Engineering, Arizona State University, Tempe, AZ, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical, Computer, and Energy Engineering, Arizona State University, Tempe, AZ, USA","institution_ids":["https://openalex.org/I55732556"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I55732556"],"apc_list":{"value":2645,"currency":"USD","value_usd":2645},"apc_paid":null,"fwci":18.033,"has_fulltext":false,"cited_by_count":350,"citation_normalized_percentile":{"value":0.99489752,"is_in_top_1_percent":true,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":96,"max":100},"biblio":{"volume":"26","issue":"7","first_page":"1354","last_page":"1367"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10036","display_name":"Advanced Neural Network Applications","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10036","display_name":"Advanced Neural Network Applications","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/stratix","display_name":"Stratix","score":0.8904141187667847},{"id":"https://openalex.org/keywords/dataflow","display_name":"Dataflow","score":0.8469744920730591},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8041383624076843},{"id":"https://openalex.org/keywords/convolutional-neural-network","display_name":"Convolutional neural network","score":0.7329214215278625},{"id":"https://openalex.org/keywords/loop-unrolling","display_name":"Loop unrolling","score":0.6994805335998535},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6947652101516724},{"id":"https://openalex.org/keywords/convolution","display_name":"Convolution (computer science)","score":0.5783298015594482},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.5358596444129944},{"id":"https://openalex.org/keywords/hardware-acceleration","display_name":"Hardware acceleration","score":0.5270949602127075},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5242505073547363},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.49340930581092834},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.47244030237197876},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3709060847759247},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3289638161659241},{"id":"https://openalex.org/keywords/artificial-neural-network","display_name":"Artificial neural network","score":0.31279581785202026},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.22837340831756592}],"concepts":[{"id":"https://openalex.org/C2776277307","wikidata":"https://www.wikidata.org/wiki/Q22074755","display_name":"Stratix","level":3,"score":0.8904141187667847},{"id":"https://openalex.org/C96324660","wikidata":"https://www.wikidata.org/wiki/Q205446","display_name":"Dataflow","level":2,"score":0.8469744920730591},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8041383624076843},{"id":"https://openalex.org/C81363708","wikidata":"https://www.wikidata.org/wiki/Q17084460","display_name":"Convolutional neural network","level":2,"score":0.7329214215278625},{"id":"https://openalex.org/C76970557","wikidata":"https://www.wikidata.org/wiki/Q1869750","display_name":"Loop unrolling","level":3,"score":0.6994805335998535},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6947652101516724},{"id":"https://openalex.org/C45347329","wikidata":"https://www.wikidata.org/wiki/Q5166604","display_name":"Convolution (computer science)","level":3,"score":0.5783298015594482},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5358596444129944},{"id":"https://openalex.org/C13164978","wikidata":"https://www.wikidata.org/wiki/Q600158","display_name":"Hardware acceleration","level":3,"score":0.5270949602127075},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5242505073547363},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.49340930581092834},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.47244030237197876},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3709060847759247},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3289638161659241},{"id":"https://openalex.org/C50644808","wikidata":"https://www.wikidata.org/wiki/Q192776","display_name":"Artificial neural network","level":2,"score":0.31279581785202026},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.22837340831756592},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2018.2815603","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2018.2815603","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G1513466694","display_name":"CAREER: Designing Ultra-Energy-Efficient Intelligent Hardware with On-Chip Learning, Attention, and Inference","funder_award_id":"1652866","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"},{"id":"https://openalex.org/G2218557206","display_name":"PFI:AIR - TT:  Improving Robustness of Nanoscale Threshold Logic based Digitial Circuits and the Performance of Design Algorithms","funder_award_id":"1701241","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"},{"id":"https://openalex.org/G2320677022","display_name":"I/UCRC FRP:  Collaborative Research: Scalable and Power-Efficient Compressive Sensing CMOS Image Sensors and Reconstruction Circuits","funder_award_id":"1535669","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"},{"id":"https://openalex.org/G4684235","display_name":"I/UCRC:  Collaborative Research: Synthesis and Design of Robust Threshold Logic Circuits","funder_award_id":"1230401","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"},{"id":"https://openalex.org/G5979266584","display_name":"SHF: Small: Efficient and Accurate Learning with Low-Precision Components: A Cortex-Inspired Approach","funder_award_id":"1715443","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"},{"id":"https://openalex.org/G7393751776","display_name":"PFI-BIC:  Novel Circuit Architectures and Design Methodologies for Low Power Digital Systems","funder_award_id":"1237856","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"},{"id":"https://openalex.org/G855719944","display_name":"I/UCRC:  Consortium for Embedded Systems - Phase II","funder_award_id":"1361926","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"}],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"},{"id":"https://openalex.org/F4320315121","display_name":"Samsung Advanced Institute of Technology","ror":"https://ror.org/04axnyp10"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":29,"referenced_works":["https://openalex.org/W1686810756","https://openalex.org/W1799366690","https://openalex.org/W2049890071","https://openalex.org/W2094756095","https://openalex.org/W2117539524","https://openalex.org/W2135252045","https://openalex.org/W2163605009","https://openalex.org/W2194775991","https://openalex.org/W2285660444","https://openalex.org/W2289252105","https://openalex.org/W2294282016","https://openalex.org/W2295680811","https://openalex.org/W2368124317","https://openalex.org/W2442974303","https://openalex.org/W2475840367","https://openalex.org/W2523838129","https://openalex.org/W2525740295","https://openalex.org/W2574797063","https://openalex.org/W2584311934","https://openalex.org/W2616014673","https://openalex.org/W2625954420","https://openalex.org/W2727238169","https://openalex.org/W2734572653","https://openalex.org/W2761085955","https://openalex.org/W2962835968","https://openalex.org/W6637373629","https://openalex.org/W6684191040","https://openalex.org/W6727533809","https://openalex.org/W6727759651"],"related_works":["https://openalex.org/W1741246166","https://openalex.org/W1508949720","https://openalex.org/W2921149022","https://openalex.org/W1855080238","https://openalex.org/W2890557332","https://openalex.org/W3048824278","https://openalex.org/W2077629192","https://openalex.org/W2996717348","https://openalex.org/W2518118925","https://openalex.org/W163022943"],"abstract_inverted_index":{"As":[0],"convolution":[1,11,78],"contributes":[2],"most":[3],"operations":[4,30],"in":[5,38],"convolutional":[6],"neural":[7],"network":[8],"(CNN),":[9],"the":[10,16,62,66,77,82,86,92,110,117,137,142,172],"acceleration":[12,134,152],"scheme":[13,153],"significantly":[14],"affects":[15],"efficiency":[17],"and":[18,28,55,69,95,108,154,165,178,185],"performance":[19],"of":[20,34,61,116,131],"a":[21,39,128],"hardware":[22,83,132],"CNN":[23,118,133,151],"accelerator.":[24],"Convolution":[25],"involves":[26],"multiply":[27],"accumulate":[29],"with":[31],"four":[32],"levels":[33],"loops,":[35],"which":[36],"results":[37],"large":[40],"design":[41,63,84,111,123],"space.":[42],"Prior":[43],"works":[44],"either":[45],"employ":[46],"limited":[47],"loop":[48,52,79],"optimization":[49,80],"techniques,":[50],"e.g.,":[51],"unrolling,":[53],"tiling,":[54],"interchange,":[56],"or":[57],"only":[58],"tune":[59],"some":[60],"variables":[64],"after":[65],"accelerator":[67,88,119],"architecture":[68,155],"dataflow":[70,130],"are":[71,156],"already":[72],"fixed.":[73],"Without":[74],"fully":[75],"studying":[76],"before":[81],"phase,":[85],"resulting":[87],"can":[89],"hardly":[90],"exploit":[91],"data":[93,97,138],"reuse":[94],"manage":[96],"movement":[98],"efficiently.":[99],"This":[100],"paper":[101],"overcomes":[102],"these":[103],"barriers":[104],"by":[105,158],"quantitatively":[106],"analyzing":[107],"optimizing":[109],"objectives":[112],"(e.g.,":[113],"memory":[114],"access)":[115],"based":[120],"on":[121,181],"multiple":[122],"variables.":[124],"Then,":[125],"we":[126],"propose":[127],"specific":[129],"to":[135,145],"minimize":[136],"communication":[139],"while":[140],"maximizing":[141],"resource":[143],"utilization":[144],"achieve":[146,175],"high":[147],"performance.":[148],"The":[149],"proposed":[150],"demonstrated":[157],"implementing":[159],"end-to-end":[160],"CNNs":[161],"including":[162],"NiN,":[163],"VGG-16,":[164],"ResNet-50/ResNet-152":[166],"for":[167],"inference.":[168],"For":[169],"VGG-16":[170],"CNN,":[171],"overall":[173],"throughputs":[174],"348":[176],"GOPS":[177,180],"715":[179],"Intel":[182],"Stratix":[183],"V":[184],"Arria":[186],"10":[187],"FPGAs,":[188],"respectively.":[189]},"counts_by_year":[{"year":2026,"cited_by_count":13},{"year":2025,"cited_by_count":39},{"year":2024,"cited_by_count":44},{"year":2023,"cited_by_count":58},{"year":2022,"cited_by_count":56},{"year":2021,"cited_by_count":54},{"year":2020,"cited_by_count":51},{"year":2019,"cited_by_count":32},{"year":2018,"cited_by_count":3}],"updated_date":"2026-08-29T07:29:34.045763","created_date":"2025-10-10T00:00:00"}
