{"id":"https://openalex.org/W2796243679","doi":"https://doi.org/10.1109/tvlsi.2018.2814627","title":"High-Performance Architecture Using Fast Dynamic Reconfigurable Accelerators","display_name":"High-Performance Architecture Using Fast Dynamic Reconfigurable Accelerators","publication_year":2018,"publication_date":"2018-04-04","ids":{"openalex":"https://openalex.org/W2796243679","doi":"https://doi.org/10.1109/tvlsi.2018.2814627","mag":"2796243679"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2018.2814627","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2018.2814627","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5063911057","display_name":"Ping-Lin Yang","orcid":"https://orcid.org/0000-0002-6723-8190"},"institutions":[{"id":"https://openalex.org/I154570441","display_name":"University of California, Santa Barbara","ror":"https://ror.org/02t274463","country_code":"US","type":"education","lineage":["https://openalex.org/I154570441"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Ping-Lin Yang","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of California at Santa Barbara, Santa Barbara, CA, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of California at Santa Barbara, Santa Barbara, CA, USA","institution_ids":["https://openalex.org/I154570441"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5063371595","display_name":"Malgorzata Marek-Sadowska","orcid":"https://orcid.org/0000-0002-3934-7031"},"institutions":[{"id":"https://openalex.org/I154570441","display_name":"University of California, Santa Barbara","ror":"https://ror.org/02t274463","country_code":"US","type":"education","lineage":["https://openalex.org/I154570441"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Malgorzata Marek-Sadowska","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of California at Santa Barbara, Santa Barbara, CA, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of California at Santa Barbara, Santa Barbara, CA, USA","institution_ids":["https://openalex.org/I154570441"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5063911057"],"corresponding_institution_ids":["https://openalex.org/I154570441"],"apc_list":null,"apc_paid":null,"fwci":0.7882,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.68947611,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"26","issue":"7","first_page":"1209","last_page":"1222"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7593137621879578},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7338798642158508},{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.6444611549377441},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.630065381526947},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.6171113848686218},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5956671237945557},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.5869446396827698},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5373403429985046},{"id":"https://openalex.org/keywords/logic-block","display_name":"Logic block","score":0.4518255591392517},{"id":"https://openalex.org/keywords/performance-improvement","display_name":"Performance improvement","score":0.42428573966026306},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.40523838996887207},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3525073528289795},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3231441378593445},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.11576783657073975}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7593137621879578},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7338798642158508},{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.6444611549377441},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.630065381526947},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.6171113848686218},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5956671237945557},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.5869446396827698},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5373403429985046},{"id":"https://openalex.org/C2778325283","wikidata":"https://www.wikidata.org/wiki/Q1125244","display_name":"Logic block","level":3,"score":0.4518255591392517},{"id":"https://openalex.org/C2778915421","wikidata":"https://www.wikidata.org/wiki/Q3643177","display_name":"Performance improvement","level":2,"score":0.42428573966026306},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.40523838996887207},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3525073528289795},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3231441378593445},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.11576783657073975},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2018.2814627","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2018.2814627","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.46000000834465027,"display_name":"Affordable and clean energy"}],"awards":[{"id":"https://openalex.org/G2196501275","display_name":null,"funder_award_id":"CNS-0960316","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"},{"id":"https://openalex.org/G2900916788","display_name":null,"funder_award_id":"CCF-1320401","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"}],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"},{"id":"https://openalex.org/F4320337367","display_name":"Division of Materials Research","ror":"https://ror.org/01pc7k308"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":56,"referenced_works":["https://openalex.org/W51968526","https://openalex.org/W1552767446","https://openalex.org/W1616249851","https://openalex.org/W1745106164","https://openalex.org/W1941487794","https://openalex.org/W1970967350","https://openalex.org/W1974274517","https://openalex.org/W1982565841","https://openalex.org/W1984105700","https://openalex.org/W1991497933","https://openalex.org/W2000036939","https://openalex.org/W2008241424","https://openalex.org/W2016461982","https://openalex.org/W2017739070","https://openalex.org/W2034024954","https://openalex.org/W2039870651","https://openalex.org/W2045617353","https://openalex.org/W2056251131","https://openalex.org/W2069234752","https://openalex.org/W2070686838","https://openalex.org/W2080804082","https://openalex.org/W2089162427","https://openalex.org/W2112813001","https://openalex.org/W2127660618","https://openalex.org/W2128337944","https://openalex.org/W2130193491","https://openalex.org/W2133027790","https://openalex.org/W2133156997","https://openalex.org/W2137978785","https://openalex.org/W2143909327","https://openalex.org/W2147657366","https://openalex.org/W2153331583","https://openalex.org/W2155814884","https://openalex.org/W2160007566","https://openalex.org/W2161903232","https://openalex.org/W2168244800","https://openalex.org/W2168635756","https://openalex.org/W2173213060","https://openalex.org/W2267836020","https://openalex.org/W2290590898","https://openalex.org/W2470243148","https://openalex.org/W2521356618","https://openalex.org/W2524556139","https://openalex.org/W2549310381","https://openalex.org/W2579431025","https://openalex.org/W2624843758","https://openalex.org/W4230706651","https://openalex.org/W4236433846","https://openalex.org/W4256629673","https://openalex.org/W4285719527","https://openalex.org/W6632992187","https://openalex.org/W6676777394","https://openalex.org/W6679149281","https://openalex.org/W6680745868","https://openalex.org/W6683776559","https://openalex.org/W6696841707"],"related_works":["https://openalex.org/W2204754129","https://openalex.org/W4322751528","https://openalex.org/W2759209791","https://openalex.org/W2034458695","https://openalex.org/W2340647897","https://openalex.org/W1541284233","https://openalex.org/W2500205862","https://openalex.org/W1569711686","https://openalex.org/W2808484818","https://openalex.org/W2129154773"],"abstract_inverted_index":{"System":[0],"accelerators":[1],"(ACCs)":[2],"improve":[3,99],"performance":[4,118,161],"and":[5,8,83,127,165,169,174,187],"break":[6],"power":[7],"utilization":[9],"walls.":[10],"They":[11],"can":[12,91,103],"be":[13,92,104],"implemented":[14],"by":[15,71,112,121],"fixed-function":[16],"hard":[17],"macros":[18],"or":[19],"reconfigurable":[20,34,57],"logic":[21],"such":[22],"as":[23],"field-programmable":[24],"gate":[25],"arrays":[26],"(FPGAs).":[27],"For":[28],"systems":[29,146],"running":[30],"various":[31,109],"applications,":[32],"dynamic":[33,56],"ACCs":[35,59,97,102,150],"offer":[36],"a":[37,63,129],"very":[38],"attractive":[39],"feature;":[40],"however,":[41],"the":[42,88],"reconfiguration":[43],"time":[44],"is":[45,69,119],"an":[46],"unavoidable":[47],"overhead.":[48],"This":[49],"paper":[50],"proposes":[51],"high-performance":[52],"architecture":[53,76,158],"with":[54,145,185,189,196],"fast":[55],"FPGA":[58,149],"(F-RACCs)":[60],"based":[61],"on":[62,162],"novel":[64],"bitstream":[65],"reprogramming":[66],"method,":[67],"which":[68],"feasible":[70],"using":[72,147,153,172],"emerging":[73],"technologies.":[74],"The":[75,101,117,135],"includes":[77],"CPU":[78,193],"cores,":[79],"caches,":[80],"memories,":[81],"ACCs,":[82],"network-on-chips.":[84],"A":[85],"portion":[86],"of":[87,115,183],"computing":[89],"tasks":[90],"offloaded":[93],"from":[94,139],"CPUs":[95],"to":[96,98,107],"performance.":[100],"reprogrammed":[105],"rapidly":[106],"accommodate":[108],"functions":[110],"required":[111],"wide":[113],"spectrum":[114],"applications.":[116],"evaluated":[120],"platform":[122],"for":[123],"ACC-rich":[124],"architectural":[125],"design":[126],"exploration,":[128],"gem5-based":[130],"cycle-accurate":[131],"full-system":[132],"simulation":[133],"platform.":[134],"11":[136],"benchmark":[137],"applications":[138,164],"different":[140],"domains":[141],"are":[142],"evaluated.":[143],"Comparing":[144],"conventional":[148],"partially":[151],"configured":[152],"fastest":[154],"configuration":[155],"speed;":[156],"this":[157],"improves":[159],"system":[160],"all":[163],"achieves":[166,180],"maximum":[167,181],"1.31\u00d7":[168],"2.82\u00d7":[170],"speedup":[171,182],"1":[173],"12":[175,190],"ACC":[176],"instances,":[177],"respectively.":[178],"It":[179],"94.93\u00d7":[184],"one":[186],"565.12\u00d7":[188],"F-RACCs":[191],"over":[192],"software":[194],"path":[195],"no":[197],"ACCs.":[198]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2018,"cited_by_count":2}],"updated_date":"2026-04-09T08:11:56.329763","created_date":"2025-10-10T00:00:00"}