{"id":"https://openalex.org/W2790711866","doi":"https://doi.org/10.1109/tvlsi.2018.2801030","title":"All-Digital Process-Variation-Calibrated Timing Generator for ATE With 1.95-ps Resolution and Maximum 1.2-GHz Test Rate","display_name":"All-Digital Process-Variation-Calibrated Timing Generator for ATE With 1.95-ps Resolution and Maximum 1.2-GHz Test Rate","publication_year":2018,"publication_date":"2018-02-14","ids":{"openalex":"https://openalex.org/W2790711866","doi":"https://doi.org/10.1109/tvlsi.2018.2801030","mag":"2790711866"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2018.2801030","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2018.2801030","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5109180346","display_name":"Dong\u2010Hoon Jung","orcid":null},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":true,"raw_author_name":"Dong-Hoon Jung","raw_affiliation_strings":["School of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea","institution_ids":["https://openalex.org/I193775966"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5084041151","display_name":"Kyungho Ryu","orcid":null},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Kyungho Ryu","raw_affiliation_strings":["School of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea","institution_ids":["https://openalex.org/I193775966"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Jung-Hyun Park","orcid":null},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Jung-Hyun Park","raw_affiliation_strings":["School of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea","institution_ids":["https://openalex.org/I193775966"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5037010076","display_name":"Seong\u2010Ook Jung","orcid":"https://orcid.org/0000-0003-0757-2581"},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Seong-Ook Jung","raw_affiliation_strings":["School of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea","institution_ids":["https://openalex.org/I193775966"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5109180346"],"corresponding_institution_ids":["https://openalex.org/I193775966"],"apc_list":null,"apc_paid":null,"fwci":0.6521,"has_fulltext":false,"cited_by_count":14,"citation_normalized_percentile":{"value":0.70084332,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":"26","issue":"6","first_page":"1015","last_page":"1025"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9966999888420105,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/clock-generator","display_name":"Clock generator","score":0.8781188726425171},{"id":"https://openalex.org/keywords/vernier-scale","display_name":"Vernier scale","score":0.772781252861023},{"id":"https://openalex.org/keywords/process-variation","display_name":"Process variation","score":0.6421040296554565},{"id":"https://openalex.org/keywords/robustness","display_name":"Robustness (evolution)","score":0.612395703792572},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5056972503662109},{"id":"https://openalex.org/keywords/generator","display_name":"Generator (circuit theory)","score":0.4913400709629059},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4541144371032715},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.35514217615127563},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3306678831577301},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.30819106101989746},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.2935965061187744},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.22404220700263977},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.20987537503242493},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.12625035643577576},{"id":"https://openalex.org/keywords/optics","display_name":"Optics","score":0.09612998366355896}],"concepts":[{"id":"https://openalex.org/C2778023540","wikidata":"https://www.wikidata.org/wiki/Q2164847","display_name":"Clock generator","level":4,"score":0.8781188726425171},{"id":"https://openalex.org/C69710193","wikidata":"https://www.wikidata.org/wiki/Q14946576","display_name":"Vernier scale","level":2,"score":0.772781252861023},{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.6421040296554565},{"id":"https://openalex.org/C63479239","wikidata":"https://www.wikidata.org/wiki/Q7353546","display_name":"Robustness (evolution)","level":3,"score":0.612395703792572},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5056972503662109},{"id":"https://openalex.org/C2780992000","wikidata":"https://www.wikidata.org/wiki/Q17016113","display_name":"Generator (circuit theory)","level":3,"score":0.4913400709629059},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4541144371032715},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.35514217615127563},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3306678831577301},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.30819106101989746},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.2935965061187744},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.22404220700263977},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.20987537503242493},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.12625035643577576},{"id":"https://openalex.org/C120665830","wikidata":"https://www.wikidata.org/wiki/Q14620","display_name":"Optics","level":1,"score":0.09612998366355896},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C104317684","wikidata":"https://www.wikidata.org/wiki/Q7187","display_name":"Gene","level":2,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2018.2801030","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2018.2801030","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8600000143051147,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W2005421687","https://openalex.org/W2021452744","https://openalex.org/W2043037338","https://openalex.org/W2043584381","https://openalex.org/W2046750594","https://openalex.org/W2065318410","https://openalex.org/W2095719743","https://openalex.org/W2096434843","https://openalex.org/W2106042087","https://openalex.org/W2118565267","https://openalex.org/W2118721819","https://openalex.org/W2126558114","https://openalex.org/W2130397798","https://openalex.org/W2134899771","https://openalex.org/W2145199955","https://openalex.org/W2147078733","https://openalex.org/W2169436946","https://openalex.org/W2788680135","https://openalex.org/W2965146426","https://openalex.org/W6661353760","https://openalex.org/W7070787922"],"related_works":["https://openalex.org/W2107482880","https://openalex.org/W2119823365","https://openalex.org/W2369998856","https://openalex.org/W2169618112","https://openalex.org/W1969806930","https://openalex.org/W2002107209","https://openalex.org/W2130851959","https://openalex.org/W1984967896","https://openalex.org/W1967032492","https://openalex.org/W2777227180"],"abstract_inverted_index":{"In":[0,31,54],"this":[1],"paper,":[2],"an":[3,10,67,121,144],"all-digital":[4],"process-variation-calibrated":[5],"high-performance":[6],"timing":[7,18,44,118,132],"generator":[8,19,45,64,70,74,119],"for":[9,24],"automatic":[11],"test":[12,123],"equipment":[13],"is":[14,79,89,109],"proposed.":[15],"The":[16,116],"proposed":[17,43,117],"generates":[20],"process-variation-tolerant":[21],"variable":[22],"delays":[23],"high":[25],"and":[26,71,81,92,143],"wide-range":[27],"testing":[28,36],"clock":[29,37],"frequency.":[30],"order":[32],"to":[33,56,128],"increase":[34],"the":[35,42,100],"frequency,":[38],"a":[39,61,72,82,131,137],"channel":[40],"of":[41,47,66,85,126,134,140,146],"consists":[46],"four":[48],"subtiming":[49],"generators":[50],"operating":[51],"in":[52,99],"parallel.":[53],"addition,":[55],"improve":[57],"process":[58],"variation":[59],"robustness,":[60],"precise":[62],"eight-phase":[63],"consisting":[65],"accurate":[68],"reference":[69],"phase":[73,83],"with":[75],"dual-loop":[76],"calibration":[77],"(CAL)":[78],"proposed,":[80],"error":[84],"less":[86],"than":[87],"1.21\u00b0":[88],"achieved.":[90],"Dynamic":[91],"static":[93],"CAL":[94],"techniques":[95],"are":[96],"also":[97],"adopted":[98],"edge":[101],"vernier.":[102],"A":[103],"prototype":[104],"chip":[105],"having":[106],"eight":[107],"channels":[108],"fabricated":[110],"using":[111],"0.13-$\\mu":[112],"\\text{m}$":[113],"CMOS":[114],"technology.":[115],"has":[120],"arbitrary":[122],"cycle":[124],"frequency":[125],"up":[127],"1.2":[129],"GHz,":[130],"resolution":[133],"1.95":[135],"ps,":[136],"power":[138],"consumption":[139],"90":[141],"mW,":[142],"area":[145],"1.5":[147],"mm":[148],"<sup":[149],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[150],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[151],".":[152]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":3},{"year":2021,"cited_by_count":2},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":1}],"updated_date":"2026-03-25T23:56:10.502304","created_date":"2025-10-10T00:00:00"}
