{"id":"https://openalex.org/W2783501794","doi":"https://doi.org/10.1109/tvlsi.2017.2785222","title":"A Reconfigurable Cache for Efficient Use of Tag RAM as Scratch-Pad Memory","display_name":"A Reconfigurable Cache for Efficient Use of Tag RAM as Scratch-Pad Memory","publication_year":2018,"publication_date":"2018-01-09","ids":{"openalex":"https://openalex.org/W2783501794","doi":"https://doi.org/10.1109/tvlsi.2017.2785222","mag":"2783501794"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2017.2785222","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2017.2785222","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5039002145","display_name":"Ing-Jer Huang","orcid":"https://orcid.org/0000-0003-0206-1010"},"institutions":[{"id":"https://openalex.org/I142974352","display_name":"National Sun Yat-sen University","ror":"https://ror.org/00mjawt10","country_code":"TW","type":"education","lineage":["https://openalex.org/I142974352"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Ing-Jer Huang","raw_affiliation_strings":["Department of Computer Science, National Sun Yat-sen University, Kaohsiung, Taiwan"],"raw_orcid":"https://orcid.org/0000-0003-0206-1010","affiliations":[{"raw_affiliation_string":"Department of Computer Science, National Sun Yat-sen University, Kaohsiung, Taiwan","institution_ids":["https://openalex.org/I142974352"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103421460","display_name":"Chun\u2010Hung Lai","orcid":null},"institutions":[{"id":"https://openalex.org/I4210148468","display_name":"Industrial Technology Research Institute","ror":"https://ror.org/05szzwt63","country_code":"TW","type":"nonprofit","lineage":["https://openalex.org/I4210148468"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chun-Hung Lai","raw_affiliation_strings":["Information and Communications Research Laboratories, Industrial Technology Research Institute, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Information and Communications Research Laboratories, Industrial Technology Research Institute, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I4210148468"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108651674","display_name":"Yun-Chung Yang","orcid":null},"institutions":[{"id":"https://openalex.org/I4210120917","display_name":"Taiwan Semiconductor Manufacturing Company (Taiwan)","ror":"https://ror.org/02wx79d08","country_code":"TW","type":"company","lineage":["https://openalex.org/I4210120917"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yun-Chung Yang","raw_affiliation_strings":["Design Validation Department, Elite Semiconductor Memory Technology Inc., Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Design Validation Department, Elite Semiconductor Memory Technology Inc., Hsinchu, Taiwan","institution_ids":["https://openalex.org/I4210120917"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5050843130","display_name":"Hsu-Kang Dow","orcid":"https://orcid.org/0000-0001-6062-9255"},"institutions":[{"id":"https://openalex.org/I142974352","display_name":"National Sun Yat-sen University","ror":"https://ror.org/00mjawt10","country_code":"TW","type":"education","lineage":["https://openalex.org/I142974352"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Hsu-Kang Dow","raw_affiliation_strings":["Department of Computer Science, National Sun Yat-sen University, Kaohsiung, Taiwan"],"raw_orcid":"https://orcid.org/0000-0001-6062-9255","affiliations":[{"raw_affiliation_string":"Department of Computer Science, National Sun Yat-sen University, Kaohsiung, Taiwan","institution_ids":["https://openalex.org/I142974352"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5063179905","display_name":"Hung-Lun Chen","orcid":null},"institutions":[{"id":"https://openalex.org/I142974352","display_name":"National Sun Yat-sen University","ror":"https://ror.org/00mjawt10","country_code":"TW","type":"education","lineage":["https://openalex.org/I142974352"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Hung-Lun Chen","raw_affiliation_strings":["Department of Computer Science, National Sun Yat-sen University, Kaohsiung, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, National Sun Yat-sen University, Kaohsiung, Taiwan","institution_ids":["https://openalex.org/I142974352"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":{"value":2645,"currency":"USD","value_usd":2645},"apc_paid":null,"fwci":0.7334,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.73561497,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"26","issue":"4","first_page":"663","last_page":"670"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8153529763221741},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.7782295346260071},{"id":"https://openalex.org/keywords/cache-coloring","display_name":"Cache coloring","score":0.6619548797607422},{"id":"https://openalex.org/keywords/cache-pollution","display_name":"Cache pollution","score":0.6390394568443298},{"id":"https://openalex.org/keywords/cache-only-memory-architecture","display_name":"Cache-only memory architecture","score":0.6201070547103882},{"id":"https://openalex.org/keywords/page-cache","display_name":"Page cache","score":0.5310302972793579},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.48151645064353943},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.46402695775032043},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4586513042449951},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.45643651485443115},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.45124030113220215},{"id":"https://openalex.org/keywords/smart-cache","display_name":"Smart Cache","score":0.4418207108974457},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.41223806142807007},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.4066769480705261},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.3732038736343384},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.3028872311115265}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8153529763221741},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.7782295346260071},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.6619548797607422},{"id":"https://openalex.org/C113166858","wikidata":"https://www.wikidata.org/wiki/Q5015981","display_name":"Cache pollution","level":5,"score":0.6390394568443298},{"id":"https://openalex.org/C3720319","wikidata":"https://www.wikidata.org/wiki/Q5015937","display_name":"Cache-only memory architecture","level":5,"score":0.6201070547103882},{"id":"https://openalex.org/C36340418","wikidata":"https://www.wikidata.org/wiki/Q7124288","display_name":"Page cache","level":5,"score":0.5310302972793579},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.48151645064353943},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.46402695775032043},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4586513042449951},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.45643651485443115},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.45124030113220215},{"id":"https://openalex.org/C167713795","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"Smart Cache","level":5,"score":0.4418207108974457},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.41223806142807007},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.4066769480705261},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.3732038736343384},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.3028872311115265}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2017.2785222","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2017.2785222","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.4399999976158142}],"awards":[{"id":"https://openalex.org/G3979186568","display_name":"The Development of Key Underlying Technologies for Computer Graphics, Video and Imaging(III)","funder_award_id":"MOST105-2218-E110-002","funder_id":"https://openalex.org/F4320322795","funder_display_name":"Ministry of Science and Technology, Taiwan"}],"funders":[{"id":"https://openalex.org/F4320322795","display_name":"Ministry of Science and Technology, Taiwan","ror":"https://ror.org/02kv4zf79"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":22,"referenced_works":["https://openalex.org/W1686420892","https://openalex.org/W2072937614","https://openalex.org/W2075190356","https://openalex.org/W2086329118","https://openalex.org/W2096867266","https://openalex.org/W2099102876","https://openalex.org/W2115171037","https://openalex.org/W2133121403","https://openalex.org/W2147657366","https://openalex.org/W2149129840","https://openalex.org/W2149590159","https://openalex.org/W2163270257","https://openalex.org/W2181961178","https://openalex.org/W2339360369","https://openalex.org/W3142248664","https://openalex.org/W3145162387","https://openalex.org/W3145738314","https://openalex.org/W4232751114","https://openalex.org/W4250251874","https://openalex.org/W6674416589","https://openalex.org/W6686014462","https://openalex.org/W6703815891"],"related_works":["https://openalex.org/W1630651028","https://openalex.org/W1929987588","https://openalex.org/W1663919135","https://openalex.org/W2109320757","https://openalex.org/W3008899932","https://openalex.org/W2062937832","https://openalex.org/W2080440721","https://openalex.org/W1891457971","https://openalex.org/W2042854674","https://openalex.org/W2544170767","https://openalex.org/W2286366494","https://openalex.org/W2123848640","https://openalex.org/W1897866642","https://openalex.org/W2541938357","https://openalex.org/W2098956068","https://openalex.org/W2419133397","https://openalex.org/W2077946042","https://openalex.org/W2119950113","https://openalex.org/W1983081937","https://openalex.org/W2037498252"],"abstract_inverted_index":{"The":[0,125,218],"cache":[1,28,47,72,89,123,195],"memory":[2,29,48,52,57,73],"has":[3,129],"been":[4,130],"a":[5,43,54,88,226],"predominant":[6],"component":[7],"in":[8,121,175,199,215],"modern":[9,36],"chips,":[10],"easily":[11],"taking":[12],"up":[13],"more":[14],"than":[15],"50%":[16],"of":[17,45,70],"the":[18,27,46,50,67,71,76,96,103,122,144,152,156,171,182,188,232],"silicon":[19],"area.":[20],"It":[21,110],"is":[22,111,185,191,225],"then":[23],"desirable":[24],"to":[25,41,99,193,230],"make":[26],"flexible":[30],"for":[31,58],"different":[32],"needs.":[33],"Therefore,":[34],"many":[35],"processor":[37],"chips":[38],"allow":[39],"users":[40],"configure":[42],"part":[44],"as":[49,102,198],"scratch-pad":[51],"(SPM),":[53],"high-speed":[55],"internal":[56],"rapid":[59],"data":[60,68],"access.":[61],"However,":[62],"such":[63,197],"approach":[64],"uses":[65],"only":[66,163],"RAM":[69,78,98],"while":[74],"leaving":[75],"tag":[77,97],"unused":[79],"and":[80,105,117,161,202],"thus":[81,106],"wasting":[82],"its":[83,108],"capacity.":[84,109],"This":[85],"paper":[86],"presents":[87],"organization,":[90],"called":[91],"Tag-SPM":[92,127,189,223],"architecture,":[93],"which":[94],"allows":[95],"be":[100,213],"used":[101],"SPM":[104,157,207,233],"increases":[107],"accomplished":[112],"with":[113,132,137],"small":[114],"Tag/Data-SPM":[115],"controllers":[116],"four":[118],"additional":[119,205],"multiplexers":[120],"organization.":[124],"proposed":[126,153],"architecture":[128,154,190,224],"implemented":[131],"an":[133],"academic":[134],"ARM-based":[135],"microprocessor":[136],"4-/4-kB":[138],"four-way":[139],"set-associative":[140],"instruction/data":[141],"caches":[142],"at":[143],"register":[145],"transfer":[146],"level":[147],"level.":[148],"Experiments":[149],"show":[150,220],"that":[151,221],"boosts":[155],"capacity":[158],"by":[159],"12.5%":[160,206],"requires":[162],"0.08%":[164],"area":[165],"(434":[166],"gates)":[167],"overhead":[168,184],"without":[169],"impairing":[170],"cache's":[172],"circuit":[173],"speed":[174],"TSMC's":[176],"90-nm":[177],"standard":[178],"cell":[179],"implementation.":[180],"Furthermore,":[181],"power":[183],"negligible.":[186],"When":[187],"applied":[192],"typical":[194],"systems,":[196],"ARM's":[200],"Cortex-A5":[201],"Cortex-A53":[203],"processors,":[204],"space":[208],"per":[209],"way":[210,229],"can":[211],"also":[212],"gained":[214],"both":[216],"cases.":[217],"analyses":[219],"our":[222],"highly":[227],"cost-effective":[228],"boost":[231],"space.":[234]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":1}],"updated_date":"2026-08-21T09:56:20.448147","created_date":"2025-10-10T00:00:00"}
