{"id":"https://openalex.org/W2767895347","doi":"https://doi.org/10.1109/tvlsi.2017.2762006","title":"Automatic Correction of Dynamic Power Management Architecture in Modern Processors","display_name":"Automatic Correction of Dynamic Power Management Architecture in Modern Processors","publication_year":2017,"publication_date":"2017-11-08","ids":{"openalex":"https://openalex.org/W2767895347","doi":"https://doi.org/10.1109/tvlsi.2017.2762006","mag":"2767895347"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2017.2762006","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2017.2762006","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5069950671","display_name":"Reza Sharafinejad","orcid":"https://orcid.org/0000-0001-6725-7001"},"institutions":[{"id":"https://openalex.org/I23946033","display_name":"University of Tehran","ror":"https://ror.org/05vf56z40","country_code":"IR","type":"education","lineage":["https://openalex.org/I23946033"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"Reza Sharafinejad","raw_affiliation_strings":["School of Electrical and Computer Engineering, College of Engineering, University of Tehran, Tehran, Iran"],"raw_orcid":"https://orcid.org/0000-0001-6725-7001","affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, College of Engineering, University of Tehran, Tehran, Iran","institution_ids":["https://openalex.org/I23946033"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5069623023","display_name":"Bijan Alizadeh","orcid":"https://orcid.org/0000-0003-4436-4597"},"institutions":[{"id":"https://openalex.org/I23946033","display_name":"University of Tehran","ror":"https://ror.org/05vf56z40","country_code":"IR","type":"education","lineage":["https://openalex.org/I23946033"]},{"id":"https://openalex.org/I4210146419","display_name":"Institute for Research in Fundamental Sciences","ror":"https://ror.org/04xreqs31","country_code":"IR","type":"facility","lineage":["https://openalex.org/I4210146419"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"Bijan Alizadeh","raw_affiliation_strings":["School of Computer Science, Institute for Research in Fundamental Sciences (IPM), Tehran, Iran","School of Electrical and Computer Engineering, College of Engineering, University of Tehran, Tehran, Iran"],"raw_orcid":"https://orcid.org/0000-0003-4436-4597","affiliations":[{"raw_affiliation_string":"School of Computer Science, Institute for Research in Fundamental Sciences (IPM), Tehran, Iran","institution_ids":["https://openalex.org/I4210146419"]},{"raw_affiliation_string":"School of Electrical and Computer Engineering, College of Engineering, University of Tehran, Tehran, Iran","institution_ids":["https://openalex.org/I23946033"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5007933406","display_name":"Zainalabedin Navabi","orcid":null},"institutions":[{"id":"https://openalex.org/I23946033","display_name":"University of Tehran","ror":"https://ror.org/05vf56z40","country_code":"IR","type":"education","lineage":["https://openalex.org/I23946033"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"Zainalabedin Navabi","raw_affiliation_strings":["School of Electrical and Computer Engineering, College of Engineering, University of Tehran, Tehran, Iran"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, College of Engineering, University of Tehran, Tehran, Iran","institution_ids":["https://openalex.org/I23946033"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":{"value":2645,"currency":"USD","value_usd":2645},"apc_paid":null,"fwci":0.3389,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.62301835,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"26","issue":"2","first_page":"308","last_page":"318"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.993399977684021,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.993399977684021,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9836000204086304,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9807000160217285,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7750619053840637},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.6998535394668579},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.6033125519752502},{"id":"https://openalex.org/keywords/counterexample","display_name":"Counterexample","score":0.603232204914093},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.5202575922012329},{"id":"https://openalex.org/keywords/dynamic-demand","display_name":"Dynamic demand","score":0.5068925023078918},{"id":"https://openalex.org/keywords/power-management","display_name":"Power management","score":0.5002021789550781},{"id":"https://openalex.org/keywords/power-gating","display_name":"Power gating","score":0.4720260202884674},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.45260822772979736},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3911958336830139},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.3441900312900543},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.332870751619339},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.19156917929649353},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.12480407953262329},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1096506416797638},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.0921148955821991}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7750619053840637},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.6998535394668579},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.6033125519752502},{"id":"https://openalex.org/C162838799","wikidata":"https://www.wikidata.org/wiki/Q596077","display_name":"Counterexample","level":2,"score":0.603232204914093},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.5202575922012329},{"id":"https://openalex.org/C45872418","wikidata":"https://www.wikidata.org/wiki/Q5318966","display_name":"Dynamic demand","level":3,"score":0.5068925023078918},{"id":"https://openalex.org/C2778774385","wikidata":"https://www.wikidata.org/wiki/Q4437810","display_name":"Power management","level":3,"score":0.5002021789550781},{"id":"https://openalex.org/C2780700455","wikidata":"https://www.wikidata.org/wiki/Q7236515","display_name":"Power gating","level":4,"score":0.4720260202884674},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.45260822772979736},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3911958336830139},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.3441900312900543},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.332870751619339},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.19156917929649353},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.12480407953262329},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1096506416797638},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0921148955821991},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C118615104","wikidata":"https://www.wikidata.org/wiki/Q121416","display_name":"Discrete mathematics","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2017.2762006","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2017.2762006","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.8100000023841858,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W1503377936","https://openalex.org/W1559753922","https://openalex.org/W1741528175","https://openalex.org/W1901827559","https://openalex.org/W1968935964","https://openalex.org/W1979903718","https://openalex.org/W1997153923","https://openalex.org/W2004023564","https://openalex.org/W2005989139","https://openalex.org/W2006853699","https://openalex.org/W2017495018","https://openalex.org/W2018320583","https://openalex.org/W2038399995","https://openalex.org/W2052943406","https://openalex.org/W2053568314","https://openalex.org/W2077890035","https://openalex.org/W2085780923","https://openalex.org/W2258744169","https://openalex.org/W2596578331","https://openalex.org/W6670324068"],"related_works":["https://openalex.org/W2972036948","https://openalex.org/W2066983888","https://openalex.org/W3009963418","https://openalex.org/W2530008369","https://openalex.org/W2152979262","https://openalex.org/W2339082925","https://openalex.org/W2053857784","https://openalex.org/W1642255152","https://openalex.org/W1990812782","https://openalex.org/W2584421631"],"abstract_inverted_index":{"The":[0,118,179],"increasing":[1],"demand":[2],"for":[3,50],"lower":[4],"power":[5,11,18,53,134,176],"forces":[6],"designers":[7,122],"to":[8,93,123,198],"use":[9],"sophisticated":[10],"management":[12,54,177],"strategies":[13],"such":[14,29,127],"as":[15,128],"multivoltage":[16],"and":[17,79,150,191,195],"gating":[19],"which":[20,111,156],"are":[21,100,157],"often":[22],"accompanied":[23],"with":[24],"many":[25],"design":[26],"bugs.":[27],"Correcting":[28],"bugs":[30,126],"can":[31],"be":[32],"a":[33,46],"time-consuming":[34],"process":[35,110],"that":[36,182],"requires":[37],"considerable":[38],"manual":[39],"efforts.":[40],"In":[41],"this":[42,95],"paper,":[43],"we":[44,85,103],"propose":[45],"scalable":[47],"automated":[48],"method":[49,120,170],"correcting":[51],"dynamic":[52],"architectures":[55],"by":[56,68,160,193],"an":[57,62,108],"incremental":[58],"SAT-based":[59],"mechanism.":[60],"First,":[61],"initial":[63],"counterexample":[64],"(CEX)":[65],"is":[66],"generated":[67],"checking":[69],"the":[70,73,77,115,138,145,166,199],"equivalency":[71],"between":[72,132],"specification":[74],"model":[75],"of":[76,91,140,168],"processor":[78],"its":[80],"buggy":[81],"implementation":[82],"model.":[83],"Then,":[84],"find":[86],"two":[87,98,133],"candidate":[88],"solutions":[89,99],"instead":[90],"one":[92],"satisfy":[94],"CEX.":[96],"If":[97],"not":[101,158],"equivalent,":[102],"generate":[104],"new":[105],"CEX":[106],"in":[107,137,144,153],"iterative":[109],"effectively":[112],"converges":[113],"into":[114],"final":[116],"solution.":[117],"proposed":[119,184],"enables":[121],"correct":[124],"multiple":[125],"missing":[129],"isolation":[130],"cells":[131],"domains,":[135],"disordering":[136],"sequence":[139],"control":[141],"signals,":[142],"error":[143],"data":[146],"restoring":[147],"or":[148],"saving,":[149],"powering":[151],"off":[152],"always-on":[154],"domains":[155],"addressed":[159],"existing":[161],"methods.":[162,201],"We":[163],"have":[164],"shown":[165],"effectiveness":[167],"our":[169,183],"on":[171],"modern":[172],"processors":[173],"supporting":[174],"complex":[175],"mechanisms.":[178],"results":[180],"confirm":[181],"method,":[185],"respectively,":[186],"reduces":[187],"symbolic":[188],"simulation":[189],"steps":[190],"runtime":[192],"2.33\u00d7":[194],"47.93\u00d7":[196],"compared":[197],"state-of-the-art":[200]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2018,"cited_by_count":2}],"updated_date":"2026-08-21T09:56:20.448147","created_date":"2025-10-10T00:00:00"}
