{"id":"https://openalex.org/W2760657028","doi":"https://doi.org/10.1109/tvlsi.2017.2752265","title":"Embedded DRAM-Based Memory Customization for Low-Cost FFT Processor Design","display_name":"Embedded DRAM-Based Memory Customization for Low-Cost FFT Processor Design","publication_year":2017,"publication_date":"2017-09-28","ids":{"openalex":"https://openalex.org/W2760657028","doi":"https://doi.org/10.1109/tvlsi.2017.2752265","mag":"2760657028"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2017.2752265","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2017.2752265","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5112384390","display_name":"Gyuseong Kang","orcid":null},"institutions":[{"id":"https://openalex.org/I197347611","display_name":"Korea University","ror":"https://ror.org/047dqcg40","country_code":"KR","type":"education","lineage":["https://openalex.org/I197347611"]}],"countries":["KR"],"is_corresponding":true,"raw_author_name":"Gyuseong Kang","raw_affiliation_strings":["School of Electrical Engineering, Korea University, Seoul, South Korea"],"affiliations":[{"raw_affiliation_string":"School of Electrical Engineering, Korea University, Seoul, South Korea","institution_ids":["https://openalex.org/I197347611"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101868841","display_name":"Woong Choi","orcid":"https://orcid.org/0000-0002-4631-7412"},"institutions":[{"id":"https://openalex.org/I197347611","display_name":"Korea University","ror":"https://ror.org/047dqcg40","country_code":"KR","type":"education","lineage":["https://openalex.org/I197347611"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Woong Choi","raw_affiliation_strings":["School of Electrical Engineering, Korea University, Seoul, South Korea"],"affiliations":[{"raw_affiliation_string":"School of Electrical Engineering, Korea University, Seoul, South Korea","institution_ids":["https://openalex.org/I197347611"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101839916","display_name":"Jongsun Park","orcid":"https://orcid.org/0000-0003-3251-0024"},"institutions":[{"id":"https://openalex.org/I197347611","display_name":"Korea University","ror":"https://ror.org/047dqcg40","country_code":"KR","type":"education","lineage":["https://openalex.org/I197347611"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Jongsun Park","raw_affiliation_strings":["School of Electrical Engineering, Korea University, Seoul, South Korea"],"affiliations":[{"raw_affiliation_string":"School of Electrical Engineering, Korea University, Seoul, South Korea","institution_ids":["https://openalex.org/I197347611"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5112384390"],"corresponding_institution_ids":["https://openalex.org/I197347611"],"apc_list":null,"apc_paid":null,"fwci":1.4794,"has_fulltext":false,"cited_by_count":17,"citation_normalized_percentile":{"value":0.83923273,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":"25","issue":"12","first_page":"3484","last_page":"3494"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9976000189781189,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9976000189781189,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10741","display_name":"Video Coding and Compression Technologies","score":0.9933000206947327,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9865999817848206,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8202091455459595},{"id":"https://openalex.org/keywords/fast-fourier-transform","display_name":"Fast Fourier transform","score":0.7148728370666504},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.6180555820465088},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5415875911712646},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5330331325531006},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.5278285145759583},{"id":"https://openalex.org/keywords/registered-memory","display_name":"Registered memory","score":0.5160315036773682},{"id":"https://openalex.org/keywords/memory-architecture","display_name":"Memory architecture","score":0.5034663081169128},{"id":"https://openalex.org/keywords/dynamic-random-access-memory","display_name":"Dynamic random-access memory","score":0.4728693664073944},{"id":"https://openalex.org/keywords/memory-refresh","display_name":"Memory refresh","score":0.4498809278011322},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.44074711203575134},{"id":"https://openalex.org/keywords/conventional-memory","display_name":"Conventional memory","score":0.440105676651001},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.4361845850944519},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.4277631938457489},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.40618646144866943},{"id":"https://openalex.org/keywords/computer-memory","display_name":"Computer memory","score":0.21238434314727783},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.09999042749404907}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8202091455459595},{"id":"https://openalex.org/C75172450","wikidata":"https://www.wikidata.org/wiki/Q623950","display_name":"Fast Fourier transform","level":2,"score":0.7148728370666504},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.6180555820465088},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5415875911712646},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5330331325531006},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.5278285145759583},{"id":"https://openalex.org/C93446704","wikidata":"https://www.wikidata.org/wiki/Q449328","display_name":"Registered memory","level":3,"score":0.5160315036773682},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.5034663081169128},{"id":"https://openalex.org/C118702147","wikidata":"https://www.wikidata.org/wiki/Q189396","display_name":"Dynamic random-access memory","level":3,"score":0.4728693664073944},{"id":"https://openalex.org/C87907426","wikidata":"https://www.wikidata.org/wiki/Q6815755","display_name":"Memory refresh","level":4,"score":0.4498809278011322},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.44074711203575134},{"id":"https://openalex.org/C53838383","wikidata":"https://www.wikidata.org/wiki/Q541148","display_name":"Conventional memory","level":5,"score":0.440105676651001},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.4361845850944519},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.4277631938457489},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.40618646144866943},{"id":"https://openalex.org/C92855701","wikidata":"https://www.wikidata.org/wiki/Q5830907","display_name":"Computer memory","level":3,"score":0.21238434314727783},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.09999042749404907}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2017.2752265","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2017.2752265","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.5}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":27,"referenced_works":["https://openalex.org/W1619268095","https://openalex.org/W1971936677","https://openalex.org/W1977482330","https://openalex.org/W1982588629","https://openalex.org/W2002293402","https://openalex.org/W2007795523","https://openalex.org/W2011596161","https://openalex.org/W2017216250","https://openalex.org/W2031948068","https://openalex.org/W2059347185","https://openalex.org/W2070905822","https://openalex.org/W2086205576","https://openalex.org/W2091764549","https://openalex.org/W2104176873","https://openalex.org/W2104865560","https://openalex.org/W2116892794","https://openalex.org/W2119667497","https://openalex.org/W2121602084","https://openalex.org/W2140196014","https://openalex.org/W2161091390","https://openalex.org/W2346685430","https://openalex.org/W2352050502","https://openalex.org/W2951920181","https://openalex.org/W2963340555","https://openalex.org/W6640442106","https://openalex.org/W6675859611","https://openalex.org/W7074706763"],"related_works":["https://openalex.org/W3048967625","https://openalex.org/W3093911585","https://openalex.org/W3185952280","https://openalex.org/W2044064773","https://openalex.org/W4248614727","https://openalex.org/W2561005478","https://openalex.org/W2296275612","https://openalex.org/W2057867585","https://openalex.org/W2612506697","https://openalex.org/W1575240748"],"abstract_inverted_index":{"In":[0,67],"this":[1],"paper,":[2],"we":[3],"present":[4],"embedded":[5],"dynamic":[6],"random":[7],"access":[8,39,111],"memory":[9,11,38,48,53,95,98],"(eDRAM)-based":[10],"customization":[12,49,54],"techniques":[13,127],"for":[14,47],"low-cost":[15],"fast":[16],"Fourier":[17],"transform":[18],"(FFT)":[19],"processor":[20,33],"design.":[21],"The":[22,52,97,134],"main":[23],"idea":[24],"is":[25,101,121],"based":[26],"on":[27],"the":[28,31,61,68,71,86,109,114,117,126,130,148,162],"observation":[29],"that":[30,147],"FFT":[32,65,132,140,165],"has":[34],"regular":[35],"and":[36,41,63,78,89,152,157],"predictable":[37],"patterns,":[40],"it":[42],"can":[43],"be":[44],"efficiently":[45],"exploited":[46],"using":[50],"eDRAM.":[51],"approaches":[55],"are":[56,82],"applied":[57],"to":[58,84,125],"both":[59],"of":[60,138],"pipelined":[62,69,131,151],"memory-based":[64,115],"architectures.":[66],"architecture,":[70,116],"read":[72],"wordline":[73,90],"(RWL)":[74],"coupling":[75],"write":[76],"assist":[77],"data":[79],"packing":[80],"schemes":[81],"employed":[83,122],"reduce":[85],"redundant":[87],"RWL":[88],"driving,":[91],"respectively,":[92],"in":[93,123,129],"columninterleaved":[94],"arrays.":[96],"address":[99],"decoder":[100],"also":[102],"simplified":[103],"with":[104,141],"thermometer":[105],"code":[106],"by":[107],"exploiting":[108],"sequential":[110],"patterns.":[112],"For":[113],"modified":[118],"cached-memory":[119,153],"structure":[120],"addition":[124],"used":[128],"architecture.":[133],"hardware":[135],"implementation":[136],"results":[137],"2k-point":[139],"a":[142],"0.11-um":[143],"CMOS":[144],"technology":[145],"show":[146],"proposed":[149],"eDRAM-based":[150],"FFTs":[154],"achieve":[155],"26.8%":[156],"33.2%":[158],"power":[159],"savings":[160],"over":[161],"static":[163],"RAM-based":[164],"design,":[166],"respectively.":[167]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":5},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":3},{"year":2018,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}