{"id":"https://openalex.org/W2762373765","doi":"https://doi.org/10.1109/tvlsi.2017.2751615","title":"Automatic Code Converter Enhanced PCH Framework for SoC Trust Verification","display_name":"Automatic Code Converter Enhanced PCH Framework for SoC Trust Verification","publication_year":2017,"publication_date":"2017-10-02","ids":{"openalex":"https://openalex.org/W2762373765","doi":"https://doi.org/10.1109/tvlsi.2017.2751615","mag":"2762373765"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2017.2751615","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2017.2751615","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5011794280","display_name":"Xiaolong Guo","orcid":"https://orcid.org/0000-0001-9896-9407"},"institutions":[{"id":"https://openalex.org/I33213144","display_name":"University of Florida","ror":"https://ror.org/02y3ad647","country_code":"US","type":"education","lineage":["https://openalex.org/I33213144"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Xiaolong Guo","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA","institution_ids":["https://openalex.org/I33213144"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081696966","display_name":"Raj Gautam Dutta","orcid":"https://orcid.org/0000-0002-5686-5666"},"institutions":[{"id":"https://openalex.org/I106165777","display_name":"University of Central Florida","ror":"https://ror.org/036nfer12","country_code":"US","type":"education","lineage":["https://openalex.org/I106165777"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Raj Gautam Dutta","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Central Florida, Orlando, FL, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Central Florida, Orlando, FL, USA","institution_ids":["https://openalex.org/I106165777"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5006818844","display_name":"Prabhat Mishra","orcid":"https://orcid.org/0000-0003-3653-6221"},"institutions":[{"id":"https://openalex.org/I33213144","display_name":"University of Florida","ror":"https://ror.org/02y3ad647","country_code":"US","type":"education","lineage":["https://openalex.org/I33213144"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Prabhat Mishra","raw_affiliation_strings":["Department of Computer and Information Science and Engineering, University of Florida, Gainesville, FL, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer and Information Science and Engineering, University of Florida, Gainesville, FL, USA","institution_ids":["https://openalex.org/I33213144"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5017464942","display_name":"Yier Jin","orcid":"https://orcid.org/0000-0002-8791-0597"},"institutions":[{"id":"https://openalex.org/I33213144","display_name":"University of Florida","ror":"https://ror.org/02y3ad647","country_code":"US","type":"education","lineage":["https://openalex.org/I33213144"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yier Jin","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA"],"raw_orcid":"https://orcid.org/0000-0002-8791-0597","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA","institution_ids":["https://openalex.org/I33213144"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.9938,"has_fulltext":false,"cited_by_count":20,"citation_normalized_percentile":{"value":0.89937547,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":"25","issue":"12","first_page":"3390","last_page":"3400"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11424","display_name":"Security and Verification in Computing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11424","display_name":"Security and Verification in Computing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11241","display_name":"Advanced Malware Detection Techniques","score":0.9965000152587891,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8296606540679932},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.7150710821151733},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.7120386362075806},{"id":"https://openalex.org/keywords/formal-verification","display_name":"Formal verification","score":0.6257561445236206},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.578953206539154},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5664204955101013},{"id":"https://openalex.org/keywords/intelligent-verification","display_name":"Intelligent verification","score":0.5106905102729797},{"id":"https://openalex.org/keywords/domain","display_name":"Domain (mathematical analysis)","score":0.4852988123893738},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.48250913619995117},{"id":"https://openalex.org/keywords/domain-specific-language","display_name":"Domain-specific language","score":0.43669408559799194},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.43534114956855774},{"id":"https://openalex.org/keywords/runtime-verification","display_name":"Runtime verification","score":0.43309688568115234},{"id":"https://openalex.org/keywords/code","display_name":"Code (set theory)","score":0.42233991622924805},{"id":"https://openalex.org/keywords/register-transfer-level","display_name":"Register-transfer level","score":0.41860824823379517},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.38383254408836365},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.37799352407455444},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.2258443534374237},{"id":"https://openalex.org/keywords/database","display_name":"Database","score":0.21515163779258728},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.19860157370567322},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.14677977561950684},{"id":"https://openalex.org/keywords/software-development","display_name":"Software development","score":0.13879871368408203},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.09563469886779785}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8296606540679932},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.7150710821151733},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.7120386362075806},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.6257561445236206},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.578953206539154},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5664204955101013},{"id":"https://openalex.org/C3406870","wikidata":"https://www.wikidata.org/wiki/Q6044160","display_name":"Intelligent verification","level":5,"score":0.5106905102729797},{"id":"https://openalex.org/C36503486","wikidata":"https://www.wikidata.org/wiki/Q11235244","display_name":"Domain (mathematical analysis)","level":2,"score":0.4852988123893738},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.48250913619995117},{"id":"https://openalex.org/C135257023","wikidata":"https://www.wikidata.org/wiki/Q691358","display_name":"Domain-specific language","level":2,"score":0.43669408559799194},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.43534114956855774},{"id":"https://openalex.org/C202973057","wikidata":"https://www.wikidata.org/wiki/Q7380130","display_name":"Runtime verification","level":3,"score":0.43309688568115234},{"id":"https://openalex.org/C2776760102","wikidata":"https://www.wikidata.org/wiki/Q5139990","display_name":"Code (set theory)","level":3,"score":0.42233991622924805},{"id":"https://openalex.org/C34854456","wikidata":"https://www.wikidata.org/wiki/Q1484552","display_name":"Register-transfer level","level":4,"score":0.41860824823379517},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.38383254408836365},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.37799352407455444},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.2258443534374237},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.21515163779258728},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.19860157370567322},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.14677977561950684},{"id":"https://openalex.org/C529173508","wikidata":"https://www.wikidata.org/wiki/Q638608","display_name":"Software development","level":3,"score":0.13879871368408203},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.09563469886779785},{"id":"https://openalex.org/C186846655","wikidata":"https://www.wikidata.org/wiki/Q3398377","display_name":"Software construction","level":4,"score":0.0},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2017.2751615","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2017.2751615","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G187319495","display_name":null,"funder_award_id":"CNS-1319105","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"},{"id":"https://openalex.org/G2923729771","display_name":null,"funder_award_id":"W911NF-17-1-0477","funder_id":"https://openalex.org/F4320338281","funder_display_name":"Army Research Office"},{"id":"https://openalex.org/G3454310977","display_name":null,"funder_award_id":"2014-TS-2554","funder_id":"https://openalex.org/F4320306087","funder_display_name":"Semiconductor Research Corporation"},{"id":"https://openalex.org/G5590119087","display_name":null,"funder_award_id":"CNS-1441667","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"}],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"},{"id":"https://openalex.org/F4320306087","display_name":"Semiconductor Research Corporation","ror":"https://ror.org/047z4n946"},{"id":"https://openalex.org/F4320338281","display_name":"Army Research Office","ror":"https://ror.org/05epdh915"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":34,"referenced_works":["https://openalex.org/W128793516","https://openalex.org/W1484614106","https://openalex.org/W1549166962","https://openalex.org/W1563456403","https://openalex.org/W1583869287","https://openalex.org/W1596552075","https://openalex.org/W1802370758","https://openalex.org/W1992787530","https://openalex.org/W2021949528","https://openalex.org/W2034711041","https://openalex.org/W2050351395","https://openalex.org/W2054362794","https://openalex.org/W2056448011","https://openalex.org/W2068118521","https://openalex.org/W2080914957","https://openalex.org/W2095144546","https://openalex.org/W2117362901","https://openalex.org/W2123205813","https://openalex.org/W2123596153","https://openalex.org/W2146412016","https://openalex.org/W2147556214","https://openalex.org/W2150928734","https://openalex.org/W2151668694","https://openalex.org/W2155843186","https://openalex.org/W2158395308","https://openalex.org/W2432335885","https://openalex.org/W2478692150","https://openalex.org/W2598542862","https://openalex.org/W3138459719","https://openalex.org/W4237770726","https://openalex.org/W6605279786","https://openalex.org/W6633843490","https://openalex.org/W6682184091","https://openalex.org/W6683354071"],"related_works":["https://openalex.org/W3036403349","https://openalex.org/W2035244079","https://openalex.org/W2962898432","https://openalex.org/W2389907042","https://openalex.org/W4301348901","https://openalex.org/W2809618173","https://openalex.org/W2528673213","https://openalex.org/W2392047570","https://openalex.org/W2350806125","https://openalex.org/W2037352836"],"abstract_inverted_index":{"The":[0],"wide":[1],"usage":[2],"of":[3,31,79,110,126,172,178],"hardware":[4,86,128,153,167],"intellectual":[5],"property":[6],"cores":[7],"from":[8,50,83,130],"untrusted":[9,84],"vendors":[10],"has":[11],"raised":[12],"security":[13,108,205],"concerns":[14],"for":[15,20,41,58,104,123,150,165],"system":[16,204],"designers.":[17],"Existing":[18],"solutions":[19,40],"functionality":[21],"testing":[22],"and":[23,53,183,202],"verification":[24,73,181,210],"do":[25],"not":[26],"usually":[27],"consider":[28],"the":[29,64,77,102,106,116,120,127,170,176],"presence":[30],"malicious":[32,43],"logic":[33],"in":[34,45,169,209],"hardware.":[35,46],"Formal":[36],"methods":[37],"provide":[38],"powerful":[39],"detecting":[42],"behaviors":[44],"However,":[47],"they":[48],"suffer":[49],"scalability":[51,65,117],"issues":[52],"cannot":[54],"be":[55],"easily":[56],"used":[57],"large-scale":[59],"computing":[60],"systems.":[61],"To":[62,174],"alleviate":[63],"challenge,":[66],"we":[67,144,188],"propose":[68],"a":[69,137,161,190,195],"new":[70],"integrated":[71,180],"formal":[72],"framework":[74,89,182],"to":[75,100,115,136,141,157],"evaluate":[76,189],"trust":[78],"system-on-chip":[80],"(SoC)":[81],"constructed":[82],"third-party":[85],"resources.":[87],"This":[88],"combines":[90],"an":[91,96,146],"automated":[92,184],"model":[93],"checker":[94],"with":[95,206],"interactive":[97],"theorem":[98],"prover":[99],"reduce":[101],"time":[103],"proving":[105],"system-level":[107],"properties":[109],"SoCs.":[111],"Another":[112],"factor":[113],"contributing":[114],"issue":[118],"is":[119,160],"effort":[121],"required":[122],"manual":[124],"conversion":[125,186],"design":[129],"register":[131],"transfer":[132],"level":[133],"(RTL)":[134],"code":[135,148,185],"domain-specific":[138],"language":[139,155,164,171],"prior":[140],"verification.":[142],"Consequently,":[143],"develop":[145],"automatic":[147],"converter":[149],"translating":[151],"VHSIC":[152],"description":[154],"(VHDL)":[156],"Formal-HDL,":[158],"which":[159],"domain":[162],"specific":[163],"representing":[166],"designs":[168],"Coq.":[173],"demonstrate":[175],"effectiveness":[177],"our":[179],"tool,":[187],"vulnerable":[191],"program":[192],"executed":[193],"on":[194],"bare":[196],"metal":[197],"LEON3":[198],"SPARC":[199],"V8":[200],"processor":[201],"prove":[203],"considerable":[207],"reduction":[208],"effort.":[211]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":6},{"year":2018,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
