{"id":"https://openalex.org/W2751272872","doi":"https://doi.org/10.1109/tvlsi.2017.2746683","title":"A 32-nm Subthreshold 7T SRAM Bit Cell With Read Assist","display_name":"A 32-nm Subthreshold 7T SRAM Bit Cell With Read Assist","publication_year":2017,"publication_date":"2017-09-08","ids":{"openalex":"https://openalex.org/W2751272872","doi":"https://doi.org/10.1109/tvlsi.2017.2746683","mag":"2751272872"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2017.2746683","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2017.2746683","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101771348","display_name":"Shourya Gupta","orcid":"https://orcid.org/0000-0002-1804-5202"},"institutions":[{"id":"https://openalex.org/I887998513","display_name":"Bharati Vidyapeeth Deemed University","ror":"https://ror.org/0052mmx10","country_code":"IN","type":"education","lineage":["https://openalex.org/I887998513"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Shourya Gupta","raw_affiliation_strings":["ECE Department, Bharati Vidyapeeth\u2019s College of Engineering, New Delhi, India","ECE Department, Bharati Vidyapeeth's College of Engineering, New Delhi, India"],"affiliations":[{"raw_affiliation_string":"ECE Department, Bharati Vidyapeeth\u2019s College of Engineering, New Delhi, India","institution_ids":["https://openalex.org/I887998513"]},{"raw_affiliation_string":"ECE Department, Bharati Vidyapeeth's College of Engineering, New Delhi, India","institution_ids":["https://openalex.org/I887998513"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5082620922","display_name":"Kirti Gupta","orcid":"https://orcid.org/0000-0003-0565-0654"},"institutions":[{"id":"https://openalex.org/I887998513","display_name":"Bharati Vidyapeeth Deemed University","ror":"https://ror.org/0052mmx10","country_code":"IN","type":"education","lineage":["https://openalex.org/I887998513"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Kirti Gupta","raw_affiliation_strings":["ECE Department, Bharati Vidyapeeth\u2019s College of Engineering, New Delhi, India","ECE Department, Bharati Vidyapeeth's College of Engineering, New Delhi, India"],"affiliations":[{"raw_affiliation_string":"ECE Department, Bharati Vidyapeeth\u2019s College of Engineering, New Delhi, India","institution_ids":["https://openalex.org/I887998513"]},{"raw_affiliation_string":"ECE Department, Bharati Vidyapeeth's College of Engineering, New Delhi, India","institution_ids":["https://openalex.org/I887998513"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5022476734","display_name":"Neeta Pandey","orcid":"https://orcid.org/0000-0003-2911-7061"},"institutions":[{"id":"https://openalex.org/I863896202","display_name":"Delhi Technological University","ror":"https://ror.org/01ztcvt22","country_code":"IN","type":"education","lineage":["https://openalex.org/I863896202"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Neeta Pandey","raw_affiliation_strings":["ECE Department, Delhi Technological University, New Delhi, India"],"affiliations":[{"raw_affiliation_string":"ECE Department, Delhi Technological University, New Delhi, India","institution_ids":["https://openalex.org/I863896202"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5101771348"],"corresponding_institution_ids":["https://openalex.org/I887998513"],"apc_list":null,"apc_paid":null,"fwci":3.7269,"has_fulltext":false,"cited_by_count":62,"citation_normalized_percentile":{"value":0.93792643,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":97,"max":100},"biblio":{"volume":"25","issue":"12","first_page":"3473","last_page":"3483"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/subthreshold-conduction","display_name":"Subthreshold conduction","score":0.7561666369438171},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.6984965801239014},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.6918103694915771},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6846001744270325},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5143364667892456},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.5126835107803345},{"id":"https://openalex.org/keywords/node","display_name":"Node (physics)","score":0.4693129062652588},{"id":"https://openalex.org/keywords/noise-margin","display_name":"Noise margin","score":0.4691644608974457},{"id":"https://openalex.org/keywords/memory-cell","display_name":"Memory cell","score":0.4653193950653076},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.4328327775001526},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.4308202564716339},{"id":"https://openalex.org/keywords/noise","display_name":"Noise (video)","score":0.4203872084617615},{"id":"https://openalex.org/keywords/margin","display_name":"Margin (machine learning)","score":0.4169021248817444},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.41640007495880127},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.38478007912635803},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.3604384958744049},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3522331118583679},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1650170087814331},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.14379560947418213}],"concepts":[{"id":"https://openalex.org/C156465305","wikidata":"https://www.wikidata.org/wiki/Q1658601","display_name":"Subthreshold conduction","level":4,"score":0.7561666369438171},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.6984965801239014},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.6918103694915771},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6846001744270325},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5143364667892456},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.5126835107803345},{"id":"https://openalex.org/C62611344","wikidata":"https://www.wikidata.org/wiki/Q1062658","display_name":"Node (physics)","level":2,"score":0.4693129062652588},{"id":"https://openalex.org/C179499742","wikidata":"https://www.wikidata.org/wiki/Q1324892","display_name":"Noise margin","level":4,"score":0.4691644608974457},{"id":"https://openalex.org/C2776638159","wikidata":"https://www.wikidata.org/wiki/Q18343761","display_name":"Memory cell","level":4,"score":0.4653193950653076},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.4328327775001526},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.4308202564716339},{"id":"https://openalex.org/C99498987","wikidata":"https://www.wikidata.org/wiki/Q2210247","display_name":"Noise (video)","level":3,"score":0.4203872084617615},{"id":"https://openalex.org/C774472","wikidata":"https://www.wikidata.org/wiki/Q6760393","display_name":"Margin (machine learning)","level":2,"score":0.4169021248817444},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.41640007495880127},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.38478007912635803},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.3604384958744049},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3522331118583679},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1650170087814331},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.14379560947418213},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0},{"id":"https://openalex.org/C66938386","wikidata":"https://www.wikidata.org/wiki/Q633538","display_name":"Structural engineering","level":1,"score":0.0},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2017.2746683","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2017.2746683","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.8999999761581421,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":23,"referenced_works":["https://openalex.org/W1549072435","https://openalex.org/W1967171495","https://openalex.org/W1968464410","https://openalex.org/W1978130618","https://openalex.org/W1983735574","https://openalex.org/W1995329733","https://openalex.org/W2036991999","https://openalex.org/W2064136443","https://openalex.org/W2073818373","https://openalex.org/W2081490067","https://openalex.org/W2095953597","https://openalex.org/W2101003251","https://openalex.org/W2111701388","https://openalex.org/W2112602631","https://openalex.org/W2114418221","https://openalex.org/W2123278390","https://openalex.org/W2131833150","https://openalex.org/W2136393784","https://openalex.org/W2162583644","https://openalex.org/W2738467824","https://openalex.org/W6676822853","https://openalex.org/W6680178178","https://openalex.org/W6682981187"],"related_works":["https://openalex.org/W2117824263","https://openalex.org/W2134421493","https://openalex.org/W3086682201","https://openalex.org/W2118528827","https://openalex.org/W2743772479","https://openalex.org/W1582224818","https://openalex.org/W2775062502","https://openalex.org/W2044270051","https://openalex.org/W4285609043","https://openalex.org/W2894151971"],"abstract_inverted_index":{"The":[0,117],"implementation":[1],"of":[2,42,65,144,158,171],"the":[3,20,34,39,43,46,105,142,145,159,178],"six-transistor":[4],"(6T)":[5],"static":[6],"random":[7],"access":[8],"memory":[9],"cell":[10,49,101,161,176],"in":[11,63,85,89,104,149,154],"deep":[12],"submicrometer":[13],"region":[14,107],"has":[15,55,136],"become":[16],"difficult":[17],"due":[18,72],"to":[19,73,109,139],"compromise":[21],"between":[22],"area,":[23],"power,":[24],"and":[25,29],"performance,":[26],"with":[27,50,112],"local":[28],"global":[30],"variations":[31],"only":[32],"exacerbating":[33],"problem":[35],"further.":[36],"To":[37,93],"impede":[38],"read-write":[40],"conflict":[41],"6T":[44],"cell,":[45],"seven-transistor":[47],"(7T)":[48],"a":[51,99,127,168],"noise-margin-free":[52],"read":[53,80,134,147],"operation":[54,81,148],"previously":[56],"been":[57,137,163],"proposed.":[58],"But":[59],"it":[60],"severely":[61,84],"lags":[62],"terms":[64],"its":[66,74],"write":[67,76,115],"ability":[68],"at":[69],"lower":[70,128],"voltages":[71],"single-ended":[75,79,146],"operation.":[77],"Its":[78],"also":[82,120],"degrades":[83],"performance":[86,143,156],"when":[87],"operating":[88],"subthreshold":[90],"(ST)":[91],"region.":[92,151],"combat":[94],"these":[95],"problems,":[96],"we":[97],"propose":[98],"7T":[100],"which":[102],"operates":[103],"ST":[106,150],"down":[108],"0.4":[110],"V":[111],"improved":[113],"dynamic":[114],"ability.":[116],"novel":[118],"topology":[119],"helps":[121],"reduce":[122],"power":[123],"consumption":[124],"by":[125],"achieving":[126,167],"data":[129],"retention":[130],"voltage":[131],"point.":[132],"A":[133],"assist":[135],"proposed":[138,160],"greatly":[140],"enhance":[141],"Large":[152],"improvements":[153],"various":[155],"metrics":[157],"have":[162],"attained":[164],"while":[165],"simultaneously":[166],"low":[169],"area":[170],"$0.254~\\mu":[172],"\\text{m}^{2}$":[173],"per":[174],"bit":[175],"on":[177],"32-nm":[179],"technology":[180],"node.":[181]},"counts_by_year":[{"year":2026,"cited_by_count":3},{"year":2025,"cited_by_count":4},{"year":2024,"cited_by_count":6},{"year":2023,"cited_by_count":6},{"year":2022,"cited_by_count":8},{"year":2021,"cited_by_count":9},{"year":2020,"cited_by_count":13},{"year":2019,"cited_by_count":6},{"year":2018,"cited_by_count":7}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}