{"id":"https://openalex.org/W2750796506","doi":"https://doi.org/10.1109/tvlsi.2017.2740343","title":"Low-Complexity Methodology for Complex Square-Root Computation","display_name":"Low-Complexity Methodology for Complex Square-Root Computation","publication_year":2017,"publication_date":"2017-08-28","ids":{"openalex":"https://openalex.org/W2750796506","doi":"https://doi.org/10.1109/tvlsi.2017.2740343","mag":"2750796506"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2017.2740343","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2017.2740343","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5035645299","display_name":"Suresh Mopuri","orcid":"https://orcid.org/0000-0002-4938-4995"},"institutions":[{"id":"https://openalex.org/I65181880","display_name":"Indian Institute of Technology Hyderabad","ror":"https://ror.org/01j4v3x97","country_code":"IN","type":"education","lineage":["https://openalex.org/I65181880"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Suresh Mopuri","raw_affiliation_strings":["Department of Electrical Engineering, IIT Hyderabad, Hyderabad, India"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, IIT Hyderabad, Hyderabad, India","institution_ids":["https://openalex.org/I65181880"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5044085104","display_name":"Amit Acharyya","orcid":"https://orcid.org/0000-0002-5636-0676"},"institutions":[{"id":"https://openalex.org/I65181880","display_name":"Indian Institute of Technology Hyderabad","ror":"https://ror.org/01j4v3x97","country_code":"IN","type":"education","lineage":["https://openalex.org/I65181880"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Amit Acharyya","raw_affiliation_strings":["Department of Electrical Engineering, IIT Hyderabad, Hyderabad, India"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, IIT Hyderabad, Hyderabad, India","institution_ids":["https://openalex.org/I65181880"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5035645299"],"corresponding_institution_ids":["https://openalex.org/I65181880"],"apc_list":null,"apc_paid":null,"fwci":1.1356,"has_fulltext":false,"cited_by_count":24,"citation_normalized_percentile":{"value":0.80395374,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":"25","issue":"11","first_page":"3255","last_page":"3259"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9958000183105469,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9929999709129333,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8588907718658447},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.7384742498397827},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6533102989196777},{"id":"https://openalex.org/keywords/cordic","display_name":"CORDIC","score":0.5813996195793152},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.55916827917099},{"id":"https://openalex.org/keywords/gate-array","display_name":"Gate array","score":0.5530616641044617},{"id":"https://openalex.org/keywords/square-root","display_name":"Square root","score":0.5254836678504944},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.5070242881774902},{"id":"https://openalex.org/keywords/computational-complexity-theory","display_name":"Computational complexity theory","score":0.4790852665901184},{"id":"https://openalex.org/keywords/virtex","display_name":"Virtex","score":0.4750273823738098},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.438973069190979},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.42700862884521484},{"id":"https://openalex.org/keywords/node","display_name":"Node (physics)","score":0.4185446500778198},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3561815619468689},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.349337637424469},{"id":"https://openalex.org/keywords/computational-science","display_name":"Computational science","score":0.3437127470970154},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.19652140140533447},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1926531195640564},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.1486484408378601}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8588907718658447},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.7384742498397827},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6533102989196777},{"id":"https://openalex.org/C58870171","wikidata":"https://www.wikidata.org/wiki/Q116076","display_name":"CORDIC","level":3,"score":0.5813996195793152},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.55916827917099},{"id":"https://openalex.org/C114237110","wikidata":"https://www.wikidata.org/wiki/Q114901","display_name":"Gate array","level":3,"score":0.5530616641044617},{"id":"https://openalex.org/C11577676","wikidata":"https://www.wikidata.org/wiki/Q134237","display_name":"Square root","level":2,"score":0.5254836678504944},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.5070242881774902},{"id":"https://openalex.org/C179799912","wikidata":"https://www.wikidata.org/wiki/Q205084","display_name":"Computational complexity theory","level":2,"score":0.4790852665901184},{"id":"https://openalex.org/C2777674469","wikidata":"https://www.wikidata.org/wiki/Q20741011","display_name":"Virtex","level":3,"score":0.4750273823738098},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.438973069190979},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.42700862884521484},{"id":"https://openalex.org/C62611344","wikidata":"https://www.wikidata.org/wiki/Q1062658","display_name":"Node (physics)","level":2,"score":0.4185446500778198},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3561815619468689},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.349337637424469},{"id":"https://openalex.org/C459310","wikidata":"https://www.wikidata.org/wiki/Q117801","display_name":"Computational science","level":1,"score":0.3437127470970154},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.19652140140533447},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1926531195640564},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1486484408378601},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C66938386","wikidata":"https://www.wikidata.org/wiki/Q633538","display_name":"Structural engineering","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2017.2740343","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2017.2740343","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8199999928474426,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[{"id":"https://openalex.org/G5834930830","display_name":null,"funder_award_id":"ECR/2015/00148","funder_id":"https://openalex.org/F4320320719","funder_display_name":"Department of Science and Technology, Ministry of Science and Technology, India"}],"funders":[{"id":"https://openalex.org/F4320320719","display_name":"Department of Science and Technology, Ministry of Science and Technology, India","ror":"https://ror.org/0101xrq71"},{"id":"https://openalex.org/F4320321071","display_name":"Department of Electronics and Information Technology, Ministry of Communications and Information Technology","ror":"https://ror.org/02z31cn83"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W1633659463","https://openalex.org/W1986797152","https://openalex.org/W1987956304","https://openalex.org/W2013238287","https://openalex.org/W2015733863","https://openalex.org/W2022431531","https://openalex.org/W2103008415","https://openalex.org/W2112173210","https://openalex.org/W2127445707","https://openalex.org/W2133033960","https://openalex.org/W2133617231","https://openalex.org/W2137828265","https://openalex.org/W2140237823","https://openalex.org/W2149785133","https://openalex.org/W2150633168","https://openalex.org/W2160751836","https://openalex.org/W2329007329","https://openalex.org/W4253978101","https://openalex.org/W6653529556","https://openalex.org/W6684301724"],"related_works":["https://openalex.org/W2361654132","https://openalex.org/W2133201231","https://openalex.org/W2261632671","https://openalex.org/W2380061327","https://openalex.org/W3010492628","https://openalex.org/W4312561048","https://openalex.org/W2380396636","https://openalex.org/W2734163423","https://openalex.org/W2750796506","https://openalex.org/W3086807857"],"abstract_inverted_index":{"In":[0],"this":[1],"brief,":[2],"we":[3],"propose":[4],"a":[5,10,16],"low-complexity":[6],"methodology":[7,48,96],"to":[8,25],"compute":[9],"complex":[11],"square":[12],"root":[13],"using":[14,55,73],"only":[15],"circular":[17,32],"coordinate":[18],"rotation":[19],"digital":[20],"computer":[21],"(CORDIC)":[22],"as":[23,33,35],"opposed":[24],"the":[26,46,52,56,94,123,128],"state-of-the-art":[27,124],"techniques":[28],"that":[29,93],"need":[30],"both":[31],"well":[34],"hyperbolic":[36],"CORDICs.":[37],"Subsequently,":[38],"an":[39],"architecture":[40],"has":[41,77],"been":[42,79],"designed":[43],"based":[44],"on":[45,51],"proposed":[47,95],"and":[49,86,106,112,132],"implemented":[50],"ASIC":[53,118],"platform":[54],"UMC":[57],"180-nm":[58],"Technology":[59],"node":[60],"with":[61,122],"1.0":[62],"V":[63],"at":[64],"5":[65],"MHz.":[66],"Field":[67],"programmable":[68],"gate":[69],"array":[70],"(FPGA)":[71],"prototyping":[72],"Xilinx'":[74],"Virtex-6":[75],"(XC6v1x240t)":[76],"also":[78],"carried":[80],"out.":[81],"After":[82],"thorough":[83],"theoretical":[84],"analysis":[85],"experimental":[87],"validations,":[88],"it":[89],"can":[90],"be":[91],"inferred":[92],"reduces":[97],"21.15%":[98],"slice":[99],"look":[100],"up":[101],"tables":[102],"(on":[103,117],"FPGA":[104],"platform)":[105,119],"saves":[107],"20.25%":[108],"silicon":[109],"area":[110],"overhead":[111],"decreases":[113],"19%":[114],"power":[115],"consumption":[116],"when":[120],"compared":[121],"method":[125],"without":[126],"compromising":[127],"computational":[129],"speed,":[130],"throughput,":[131],"accuracy.":[133]},"counts_by_year":[{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":6},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":4},{"year":2021,"cited_by_count":4},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}