{"id":"https://openalex.org/W2741248434","doi":"https://doi.org/10.1109/tvlsi.2017.2729884","title":"Low-Power 19-Transistor True Single-Phase Clocking Flip-Flop Design Based on Logic Structure Reduction Schemes","display_name":"Low-Power 19-Transistor True Single-Phase Clocking Flip-Flop Design Based on Logic Structure Reduction Schemes","publication_year":2017,"publication_date":"2017-07-31","ids":{"openalex":"https://openalex.org/W2741248434","doi":"https://doi.org/10.1109/tvlsi.2017.2729884","mag":"2741248434"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2017.2729884","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2017.2729884","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5000277158","display_name":"Jin\u2010Fa Lin","orcid":"https://orcid.org/0000-0001-6240-6055"},"institutions":[{"id":"https://openalex.org/I126145234","display_name":"Chaoyang University of Technology","ror":"https://ror.org/04xwksx09","country_code":"TW","type":"education","lineage":["https://openalex.org/I126145234"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Jin-Fa Lin","raw_affiliation_strings":["Department of Information and Communication Engineering, Chaoyang University of Technology, Taichung, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Information and Communication Engineering, Chaoyang University of Technology, Taichung, Taiwan","institution_ids":["https://openalex.org/I126145234"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5019598631","display_name":"Ming\u2010Hwa Sheu","orcid":"https://orcid.org/0000-0002-8417-474X"},"institutions":[{"id":"https://openalex.org/I75357094","display_name":"National Yunlin University of Science and Technology","ror":"https://ror.org/04qkq2m54","country_code":"TW","type":"education","lineage":["https://openalex.org/I75357094"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Ming-Hwa Sheu","raw_affiliation_strings":["Department of Electronic Engineering, National Yunlin University of Science and Technology, Douliu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, National Yunlin University of Science and Technology, Douliu, Taiwan","institution_ids":["https://openalex.org/I75357094"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5019252212","display_name":"Yin\u2010Tsung Hwang","orcid":"https://orcid.org/0000-0001-9233-0477"},"institutions":[{"id":"https://openalex.org/I162838928","display_name":"National Chung Hsing University","ror":"https://ror.org/05vn3ca78","country_code":"TW","type":"education","lineage":["https://openalex.org/I162838928"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yin-Tsung Hwang","raw_affiliation_strings":["Department of Electrical Engineering, National Chung Hsing University, Taichung, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Chung Hsing University, Taichung, Taiwan","institution_ids":["https://openalex.org/I162838928"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5071056199","display_name":"Chen\u2010Syuan Wong","orcid":null},"institutions":[{"id":"https://openalex.org/I75357094","display_name":"National Yunlin University of Science and Technology","ror":"https://ror.org/04qkq2m54","country_code":"TW","type":"education","lineage":["https://openalex.org/I75357094"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chen-Syuan Wong","raw_affiliation_strings":["Department of Electronic Engineering, National Yunlin University of Science and Technology, Douliu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, National Yunlin University of Science and Technology, Douliu, Taiwan","institution_ids":["https://openalex.org/I75357094"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5086018774","display_name":"Ming-Yan Tsai","orcid":null},"institutions":[{"id":"https://openalex.org/I75357094","display_name":"National Yunlin University of Science and Technology","ror":"https://ror.org/04qkq2m54","country_code":"TW","type":"education","lineage":["https://openalex.org/I75357094"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Ming-Yan Tsai","raw_affiliation_strings":["Department of Electronic Engineering, National Yunlin University of Science and Technology, Douliu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, National Yunlin University of Science and Technology, Douliu, Taiwan","institution_ids":["https://openalex.org/I75357094"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5000277158"],"corresponding_institution_ids":["https://openalex.org/I126145234"],"apc_list":null,"apc_paid":null,"fwci":3.5836,"has_fulltext":false,"cited_by_count":71,"citation_normalized_percentile":{"value":0.93458181,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":97,"max":99},"biblio":{"volume":"25","issue":"11","first_page":"3033","last_page":"3044"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/flip-flop","display_name":"Flip-flop","score":0.7236301898956299},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.6013523936271667},{"id":"https://openalex.org/keywords/transmission-gate","display_name":"Transmission gate","score":0.600967288017273},{"id":"https://openalex.org/keywords/process-corners","display_name":"Process corners","score":0.5506179928779602},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.5490342974662781},{"id":"https://openalex.org/keywords/power\u2013delay-product","display_name":"Power\u2013delay product","score":0.5430417060852051},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.538321316242218},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5266427993774414},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4648849666118622},{"id":"https://openalex.org/keywords/transistor-count","display_name":"Transistor count","score":0.46393898129463196},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4576590955257416},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.4242382049560547},{"id":"https://openalex.org/keywords/leakage","display_name":"Leakage (economics)","score":0.42111748456954956},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3730376958847046},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2914472222328186},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.28159523010253906},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.1099058985710144}],"concepts":[{"id":"https://openalex.org/C2781007278","wikidata":"https://www.wikidata.org/wiki/Q183406","display_name":"Flip-flop","level":3,"score":0.7236301898956299},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.6013523936271667},{"id":"https://openalex.org/C2780949067","wikidata":"https://www.wikidata.org/wiki/Q1136752","display_name":"Transmission gate","level":4,"score":0.600967288017273},{"id":"https://openalex.org/C192615534","wikidata":"https://www.wikidata.org/wiki/Q7247268","display_name":"Process corners","level":3,"score":0.5506179928779602},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.5490342974662781},{"id":"https://openalex.org/C2776391166","wikidata":"https://www.wikidata.org/wiki/Q7236873","display_name":"Power\u2013delay product","level":4,"score":0.5430417060852051},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.538321316242218},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5266427993774414},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4648849666118622},{"id":"https://openalex.org/C196320899","wikidata":"https://www.wikidata.org/wiki/Q2623746","display_name":"Transistor count","level":4,"score":0.46393898129463196},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4576590955257416},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.4242382049560547},{"id":"https://openalex.org/C2777042071","wikidata":"https://www.wikidata.org/wiki/Q6509304","display_name":"Leakage (economics)","level":2,"score":0.42111748456954956},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3730376958847046},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2914472222328186},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.28159523010253906},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.1099058985710144},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2017.2729884","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2017.2729884","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8299999833106995,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[{"id":"https://openalex.org/G4439308463","display_name":null,"funder_award_id":"105-2221-E-324-023","funder_id":"https://openalex.org/F4320322795","funder_display_name":"Ministry of Science and Technology, Taiwan"}],"funders":[{"id":"https://openalex.org/F4320322795","display_name":"Ministry of Science and Technology, Taiwan","ror":"https://ror.org/02kv4zf79"},{"id":"https://openalex.org/F4320323022","display_name":"National Chung-Hsing University","ror":"https://ror.org/05vn3ca78"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W2039473024","https://openalex.org/W2047694997","https://openalex.org/W2056378213","https://openalex.org/W2068316116","https://openalex.org/W2099569658","https://openalex.org/W2100868372","https://openalex.org/W2109195618","https://openalex.org/W2109769819","https://openalex.org/W2127639550","https://openalex.org/W2128218350","https://openalex.org/W2137616964","https://openalex.org/W2145876393","https://openalex.org/W2149778532","https://openalex.org/W2164002677","https://openalex.org/W2170265438","https://openalex.org/W3089937351","https://openalex.org/W3149410719","https://openalex.org/W4237249613","https://openalex.org/W4247612443","https://openalex.org/W6681475482","https://openalex.org/W6819126557"],"related_works":["https://openalex.org/W2611474147","https://openalex.org/W2899979858","https://openalex.org/W2981473605","https://openalex.org/W4310090211","https://openalex.org/W3208898872","https://openalex.org/W4391113205","https://openalex.org/W2425031246","https://openalex.org/W2050324876","https://openalex.org/W1977149530","https://openalex.org/W2741248434"],"abstract_inverted_index":{"In":[0,39,80,104,129],"this":[1,81,130],"paper,":[2,131],"an":[3],"ultralow-power":[4],"true":[5],"single-phase":[6],"clocking":[7],"flip-flop":[8],"(FF)":[9],"design":[10,19,30,86,157,177,199,231],"achieved":[11],"using":[12],"only":[13],"19":[14],"transistors":[15,54],"is":[16,47,98],"proposed.":[17],"The":[18,141],"follows":[20],"a":[21,27,42,83,90],"master-slave-type":[22],"logic":[23,29,34,43],"structure":[24,44],"and":[25,35,59,171,208,223],"features":[26],"hybrid":[28],"comprising":[31],"both":[32],"static-CMOS":[33],"complementary":[36],"pass-transistor":[37],"logic.":[38],"the":[40,51,73,95,114,126,132,155,176,182,188,193,197,209,230],"design,":[41,82,192],"reduction":[45],"scheme":[46],"employed":[48],"to":[49,75,100,113,180,202,228],"reduce":[50],"number":[52],"of":[53,135,144],"for":[55],"achieving":[56],"high":[57],"power":[58,78,169,173],"delay":[60],"performance.":[61,103],"Despite":[62],"its":[63],"circuit":[64,105],"simplicity,":[65],"no":[66],"internal":[67],"nodes":[68],"are":[69,109],"left":[70],"floating":[71],"during":[72],"operation":[74],"avoid":[76],"leakage":[77,172],"consumption.":[79,174],"virtual":[84],"VDD":[85],"technique,":[87],"which":[88],"facilitates":[89],"faster":[91],"state":[92],"transition":[93],"in":[94,159,196],"slave":[96],"latch,":[97],"devised":[99],"enhance":[101],"time":[102],"implementation,":[106],"transistor":[107],"sizes":[108],"optimized":[110],"with":[111,187],"respect":[112],"powerdelay":[115],"product":[116],"(PDP).":[117],"A":[118],"TSMC":[119],"90-nm":[120],"CMOS":[121],"process":[122,218],"was":[123,178,200,212],"selected":[124],"as":[125,164],"implementation":[127],"technology.":[128],"performance":[133,161],"levels":[134],"seven":[136],"FF":[137,146,191],"designs":[138],"were":[139,147,226],"compared.":[140],"timing":[142],"parameters":[143],"each":[145],"first":[148],"characterized.":[149],"Post-layout":[150],"simulation":[151],"results":[152],"indicated":[153],"that":[154],"proposed":[156,198],"excelled":[158],"various":[160],"indices":[162],"such":[163],"PDP,":[165],"clock-to-Q":[166],"delay,":[167],"average":[168],"consumption,":[170],"Moreover,":[175],"determined":[179],"have":[181],"smallest":[183],"layout":[184],"area.":[185],"Compared":[186],"conventional":[189],"transmission-gate-based":[190],"PDP":[194],"improvement":[195],"up":[201],"63.5%":[203],"(at":[204],"12.5%":[205],"switching":[206],"activity)":[207],"area":[210],"saving":[211],"approximately":[213],"10%.":[214],"Further":[215],"simulations":[216],"on":[217],"corners,":[219],"supply":[220],"voltage":[221],"settings,":[222],"working":[224],"frequencies":[225],"conducted":[227],"study":[229],"reliability.":[232]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":6},{"year":2024,"cited_by_count":11},{"year":2023,"cited_by_count":8},{"year":2022,"cited_by_count":10},{"year":2021,"cited_by_count":10},{"year":2020,"cited_by_count":8},{"year":2019,"cited_by_count":9},{"year":2018,"cited_by_count":8}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}