{"id":"https://openalex.org/W2708719778","doi":"https://doi.org/10.1109/tvlsi.2017.2712804","title":"Using a Device State Library to Boost the Performance of TCAD Mixed-Mode Simulation","display_name":"Using a Device State Library to Boost the Performance of TCAD Mixed-Mode Simulation","publication_year":2017,"publication_date":"2017-06-23","ids":{"openalex":"https://openalex.org/W2708719778","doi":"https://doi.org/10.1109/tvlsi.2017.2712804","mag":"2708719778"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2017.2712804","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2017.2712804","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5080137972","display_name":"Xiaoliang Dai","orcid":"https://orcid.org/0000-0003-3098-2714"},"institutions":[{"id":"https://openalex.org/I20089843","display_name":"Princeton University","ror":"https://ror.org/00hx57361","country_code":"US","type":"education","lineage":["https://openalex.org/I20089843"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Xiaoliang Dai","raw_affiliation_strings":["Department of Electrical Engineering, Princeton University, Princeton, NJ, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Princeton University, Princeton, NJ, USA","institution_ids":["https://openalex.org/I20089843"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5086131079","display_name":"Niraj K. Jha","orcid":"https://orcid.org/0000-0002-1539-0369"},"institutions":[{"id":"https://openalex.org/I20089843","display_name":"Princeton University","ror":"https://ror.org/00hx57361","country_code":"US","type":"education","lineage":["https://openalex.org/I20089843"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Niraj K. Jha","raw_affiliation_strings":["Department of Electrical Engineering, Princeton University, Princeton, NJ, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Princeton University, Princeton, NJ, USA","institution_ids":["https://openalex.org/I20089843"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5080137972"],"corresponding_institution_ids":["https://openalex.org/I20089843"],"apc_list":null,"apc_paid":null,"fwci":0.1469,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.49245105,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"25","issue":"9","first_page":"2616","last_page":"2624"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6903980374336243},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.6553439497947693},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.6367809176445007},{"id":"https://openalex.org/keywords/leverage","display_name":"Leverage (statistics)","score":0.5607821941375732},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.5230315923690796},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.47138720750808716},{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.45657777786254883},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.44837626814842224},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4239775538444519},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.40670159459114075},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3277313709259033},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.3273288607597351},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.23658618330955505},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.2137449085712433},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.19849365949630737},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.17483362555503845}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6903980374336243},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.6553439497947693},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.6367809176445007},{"id":"https://openalex.org/C153083717","wikidata":"https://www.wikidata.org/wiki/Q6535263","display_name":"Leverage (statistics)","level":2,"score":0.5607821941375732},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.5230315923690796},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.47138720750808716},{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.45657777786254883},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.44837626814842224},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4239775538444519},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.40670159459114075},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3277313709259033},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.3273288607597351},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.23658618330955505},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.2137449085712433},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.19849365949630737},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.17483362555503845},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2017.2712804","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2017.2712804","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G6463810614","display_name":null,"funder_award_id":"CCF-1217076","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"}],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W1987828367","https://openalex.org/W1991353080","https://openalex.org/W2035568159","https://openalex.org/W2046963801","https://openalex.org/W2054002802","https://openalex.org/W2063513484","https://openalex.org/W2097797048","https://openalex.org/W2118116654","https://openalex.org/W2119496526","https://openalex.org/W2135189649","https://openalex.org/W2159336103","https://openalex.org/W2160367182","https://openalex.org/W2167135674","https://openalex.org/W2172215492","https://openalex.org/W2219433894","https://openalex.org/W2293989840","https://openalex.org/W2406413704","https://openalex.org/W4235300956","https://openalex.org/W4300179460","https://openalex.org/W6679969737","https://openalex.org/W6683783425"],"related_works":["https://openalex.org/W2610514210","https://openalex.org/W90892980","https://openalex.org/W2031753133","https://openalex.org/W2080129643","https://openalex.org/W2051041430","https://openalex.org/W2151657833","https://openalex.org/W1554205582","https://openalex.org/W3111996845","https://openalex.org/W2126379574","https://openalex.org/W2093491063"],"abstract_inverted_index":{"Technology":[0],"computer-aided":[1],"design":[2],"(TCAD)":[3],"device":[4,70,79],"and":[5,11,18,37,45,126,132],"small":[6],"circuit":[7],"simulations":[8,28,95],"use":[9,69],"numerical":[10],"physics":[12],"models":[13],"to":[14,64,76,87,106],"investigate":[15],"the":[16,100,136],"properties":[17],"performance":[19],"of":[20],"circuits":[21],"before":[22],"they":[23,40],"undergo":[24],"fabrication.":[25],"Thus,":[26],"these":[27],"play":[29],"a":[30,60,78,89,107,122,127],"significant":[31,108],"role":[32],"in":[33],"VLSI":[34],"design,":[35],"optimization,":[36],"verification.":[38],"However,":[39],"suffer":[41],"from":[42,73],"poor":[43],"convergence":[44],"high":[46],"CPU":[47,137],"times,":[48],"especially":[49],"when":[50],"performing":[51],"TCAD":[52],"mixed-mode":[53],"simulations.":[54],"In":[55],"this":[56,66],"paper,":[57],"we":[58,83],"propose":[59],"new":[61],"simulation":[62],"flow":[63],"address":[65],"challenge.":[67],"We":[68],"states":[71],"captured":[72],"single":[74],"devices":[75],"build":[77],"state":[80],"library.":[81],"Then,":[82],"leverage":[84],"device-level":[85],"solutions":[86],"form":[88],"global":[90],"initial":[91],"guess":[92],"for":[93,114,121,139],"circuit-level":[94],"that":[96],"are":[97],"based":[98],"on":[99],"full":[101],"Newton":[102],"algorithm.":[103],"This":[104],"leads":[105],"efficiency":[109],"enhancement.":[110],"The":[111],"average":[112],"speedup":[113],"quasi-stationary":[115],"(or":[116],"dc)":[117],"operating":[118],"point":[119],"establishment":[120],"standard":[123],"cell":[124],"library":[125],"mirror":[128],"adder":[129],"is":[130,148],"6.9\u00d7":[131],"21.2\u00d7,":[133],"respectively,":[134],"whereas":[135],"time":[138],"static":[140,144],"random":[141],"access":[142],"memory":[143],"noise":[145],"margin":[146],"extraction":[147],"reduced":[149],"by":[150],"47.0%.":[151]},"counts_by_year":[{"year":2019,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
