{"id":"https://openalex.org/W2612563535","doi":"https://doi.org/10.1109/tvlsi.2017.2691409","title":"Leveraging Unused Resources for Energy Optimization of FPGA Interconnect","display_name":"Leveraging Unused Resources for Energy Optimization of FPGA Interconnect","publication_year":2017,"publication_date":"2017-05-12","ids":{"openalex":"https://openalex.org/W2612563535","doi":"https://doi.org/10.1109/tvlsi.2017.2691409","mag":"2612563535"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2017.2691409","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2017.2691409","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5075152320","display_name":"Safeen Huda","orcid":"https://orcid.org/0000-0001-8391-0509"},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Safeen Huda","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Toronto, Toronto, ON, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Toronto, Toronto, ON, Canada","institution_ids":["https://openalex.org/I185261750"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5102812429","display_name":"Jason H. Anderson","orcid":"https://orcid.org/0000-0001-9083-6853"},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Jason H. Anderson","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Toronto, Toronto, ON, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Toronto, Toronto, ON, Canada","institution_ids":["https://openalex.org/I185261750"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5075152320"],"corresponding_institution_ids":["https://openalex.org/I185261750"],"apc_list":null,"apc_paid":null,"fwci":0.5734,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.68623684,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"25","issue":"8","first_page":"2307","last_page":"2320"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5801987648010254},{"id":"https://openalex.org/keywords/dynamic-demand","display_name":"Dynamic demand","score":0.5734453797340393},{"id":"https://openalex.org/keywords/equal-cost-multi-path-routing","display_name":"Equal-cost multi-path routing","score":0.5374608039855957},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.5350794196128845},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.4989185333251953},{"id":"https://openalex.org/keywords/static-routing","display_name":"Static routing","score":0.3602569103240967},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.33306965231895447},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.30391356348991394},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2858123183250427},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.2768843173980713},{"id":"https://openalex.org/keywords/routing-protocol","display_name":"Routing protocol","score":0.16139858961105347},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.07275253534317017}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5801987648010254},{"id":"https://openalex.org/C45872418","wikidata":"https://www.wikidata.org/wiki/Q5318966","display_name":"Dynamic demand","level":3,"score":0.5734453797340393},{"id":"https://openalex.org/C115443555","wikidata":"https://www.wikidata.org/wiki/Q5367790","display_name":"Equal-cost multi-path routing","level":5,"score":0.5374608039855957},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.5350794196128845},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.4989185333251953},{"id":"https://openalex.org/C204948658","wikidata":"https://www.wikidata.org/wiki/Q1119410","display_name":"Static routing","level":4,"score":0.3602569103240967},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.33306965231895447},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.30391356348991394},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2858123183250427},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.2768843173980713},{"id":"https://openalex.org/C104954878","wikidata":"https://www.wikidata.org/wiki/Q1648707","display_name":"Routing protocol","level":3,"score":0.16139858961105347},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.07275253534317017},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2017.2691409","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2017.2691409","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8899999856948853,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320334593","display_name":"Natural Sciences and Engineering Research Council of Canada","ror":"https://ror.org/01h531d29"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":30,"referenced_works":["https://openalex.org/W1481987700","https://openalex.org/W1524957862","https://openalex.org/W1542337393","https://openalex.org/W1924383472","https://openalex.org/W1970278706","https://openalex.org/W1977850862","https://openalex.org/W1984163339","https://openalex.org/W2001824086","https://openalex.org/W2005602803","https://openalex.org/W2008852833","https://openalex.org/W2030765577","https://openalex.org/W2041557219","https://openalex.org/W2074599790","https://openalex.org/W2097207701","https://openalex.org/W2097683623","https://openalex.org/W2098958982","https://openalex.org/W2115150830","https://openalex.org/W2117953147","https://openalex.org/W2128473621","https://openalex.org/W2131862714","https://openalex.org/W2135987877","https://openalex.org/W2137978438","https://openalex.org/W2264331490","https://openalex.org/W2275304190","https://openalex.org/W2395647080","https://openalex.org/W4256629673","https://openalex.org/W6640213617","https://openalex.org/W6642590662","https://openalex.org/W6675087722","https://openalex.org/W6693634651"],"related_works":["https://openalex.org/W2133528131","https://openalex.org/W1968523244","https://openalex.org/W3001354221","https://openalex.org/W1561162933","https://openalex.org/W103514590","https://openalex.org/W2306651031","https://openalex.org/W1998565297","https://openalex.org/W1529990755","https://openalex.org/W2767163512","https://openalex.org/W1977807074"],"abstract_inverted_index":{"Conventional":[0],"field-programmable":[1],"gate":[2],"arrays":[3],"are":[4,53,60,101,120,192],"typically":[5],"overprovisioned":[6],"with":[7,140,194],"routing":[8,21,33,51,57,81,90,129,159],"resources":[9],"to":[10,35,47,55,63,94,122,151,174,182],"ensure":[11,48,116],"that":[12,49,78,117,167],"they":[13],"meet":[14],"routeability":[15],"targets,":[16],"which":[17,59,92],"results":[18],"in":[19,80,157],"increased":[20],"static":[22,39,74,177],"and":[23,38,103,131,143,184,201],"dynamic":[24,37,43,169],"power.":[25,40],"In":[26],"this":[27],"paper,":[28],"we":[29,45,76,133],"leverage":[30],"the":[31,65,89,95,106,109,125,153,158,162],"excess":[32],"conductors":[34,52,119],"reduce":[36,42,64,73],"To":[41,72,115],"power,":[44,75],"propose":[46,134],"used":[50],"adjacent":[54],"unused":[56,102,118],"conductors,":[58,91],"left":[61,104],"floating":[62],"effective":[66],"capacitance":[67],"seen":[68],"by":[69,85],"active":[70],"nets.":[71],"observe":[77],"leakage":[79,107],"multiplexers":[82],"is":[83],"dominated":[84],"specific":[86],"paths;":[87],"if":[88],"connect":[93],"input":[96],"pins":[97],"on":[98],"these":[99],"paths,":[100],"floating,":[105],"of":[108,127,172,180,199,203],"multiplexer":[110],"may":[111],"be":[112],"significantly":[113],"reduced.":[114],"allowed":[121],"float":[123],"requires":[124],"use":[126],"tristate":[128,137],"buffers,":[130],"thus":[132],"two":[135],"low-cost":[136],"buffer":[138],"topologies":[139],"different":[141],"power":[142,170,178],"area-overhead":[144,202],"tradeoffs.":[145],"We":[146],"also":[147],"introduce":[148],"CAD":[149],"techniques":[150],"optimize":[152],"overall":[154,185],"energy":[155,187],"dissipation":[156],"network":[160],"using":[161],"proposed":[163],"techniques.":[164],"Results":[165],"show":[166],"interconnect":[168,176,186],"reductions":[171,179,188],"up":[173,181],"25%,":[175],"81%,":[183],"ranging":[189],"between":[190],"14.9%-42.7%":[191],"expected,":[193],"a":[195],"critical":[196],"path":[197],"degradation":[198],"<;1.8%":[200],"2.6%-4.8%.":[204]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}