{"id":"https://openalex.org/W2586553551","doi":"https://doi.org/10.1109/tvlsi.2017.2652482","title":"Error-Resilient Integrated Clock Gate for Clock-Tree Power Optimization on a Wide Voltage IOT Processor","display_name":"Error-Resilient Integrated Clock Gate for Clock-Tree Power Optimization on a Wide Voltage IOT Processor","publication_year":2017,"publication_date":"2017-02-07","ids":{"openalex":"https://openalex.org/W2586553551","doi":"https://doi.org/10.1109/tvlsi.2017.2652482","mag":"2586553551"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2017.2652482","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2017.2652482","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100717935","display_name":"\u03a4ao Zhu","orcid":"https://orcid.org/0000-0003-0228-3916"},"institutions":[{"id":"https://openalex.org/I76130692","display_name":"Zhejiang University","ror":"https://ror.org/00a2xv884","country_code":"CN","type":"education","lineage":["https://openalex.org/I76130692"]},{"id":"https://openalex.org/I4210092088","display_name":"Zhejiang Province Institute of Architectural Design and Research","ror":"https://ror.org/00f89ms08","country_code":"CN","type":"facility","lineage":["https://openalex.org/I4210092088"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Tao-Tao Zhu","raw_affiliation_strings":["Institute of VLSI Design, Zhejiang University, Hangzhou, China"],"affiliations":[{"raw_affiliation_string":"Institute of VLSI Design, Zhejiang University, Hangzhou, China","institution_ids":["https://openalex.org/I4210092088","https://openalex.org/I76130692"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5022767878","display_name":"Jianyi Meng","orcid":null},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jian-Yi Meng","raw_affiliation_strings":["State Key Laboratory of ASIC and System, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5046536624","display_name":"Xiaoyan Xiang","orcid":"https://orcid.org/0000-0002-5602-2749"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xiao-Yan Xiang","raw_affiliation_strings":["State Key Laboratory of ASIC and System, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101586250","display_name":"Xiaolang Yan","orcid":"https://orcid.org/0000-0003-2284-3036"},"institutions":[{"id":"https://openalex.org/I4210092088","display_name":"Zhejiang Province Institute of Architectural Design and Research","ror":"https://ror.org/00f89ms08","country_code":"CN","type":"facility","lineage":["https://openalex.org/I4210092088"]},{"id":"https://openalex.org/I76130692","display_name":"Zhejiang University","ror":"https://ror.org/00a2xv884","country_code":"CN","type":"education","lineage":["https://openalex.org/I76130692"]},{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xiao-Lang Yan","raw_affiliation_strings":["Institute of VLSI Design, Zhejiang University, Hangzhou, China","State Key Laboratory of ASIC and System, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"Institute of VLSI Design, Zhejiang University, Hangzhou, China","institution_ids":["https://openalex.org/I4210092088","https://openalex.org/I76130692"]},{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5100717935"],"corresponding_institution_ids":["https://openalex.org/I4210092088","https://openalex.org/I76130692"],"apc_list":null,"apc_paid":null,"fwci":0.2867,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.56746136,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"25","issue":"5","first_page":"1681","last_page":"1693"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5884870886802673},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.5528240203857422},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.46489256620407104},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.45979687571525574},{"id":"https://openalex.org/keywords/spice","display_name":"Spice","score":0.4356456995010376},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.43381279706954956},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.38526737689971924},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2945408523082733},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.25378894805908203},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.23284175992012024},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.188815176486969}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5884870886802673},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.5528240203857422},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.46489256620407104},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.45979687571525574},{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.4356456995010376},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.43381279706954956},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.38526737689971924},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2945408523082733},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.25378894805908203},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.23284175992012024},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.188815176486969},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2017.2652482","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2017.2652482","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.9100000262260437,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[{"id":"https://openalex.org/G1014697965","display_name":null,"funder_award_id":"15ZR1402700","funder_id":"https://openalex.org/F4320321885","funder_display_name":"Science and Technology Commission of Shanghai Municipality"},{"id":"https://openalex.org/G1766942847","display_name":null,"funder_award_id":"2015KF009","funder_id":"https://openalex.org/F4320321851","funder_display_name":"Fudan University"},{"id":"https://openalex.org/G3398006070","display_name":null,"funder_award_id":"2015AA016601","funder_id":"https://openalex.org/F4320321540","funder_display_name":"Ministry of Science and Technology of the People's Republic of China"},{"id":"https://openalex.org/G708859151","display_name":null,"funder_award_id":"2015ZD005","funder_id":"https://openalex.org/F4320321851","funder_display_name":"Fudan University"}],"funders":[{"id":"https://openalex.org/F4320321540","display_name":"Ministry of Science and Technology of the People's Republic of China","ror":"https://ror.org/027s68j25"},{"id":"https://openalex.org/F4320321851","display_name":"Fudan University","ror":"https://ror.org/013q1eq08"},{"id":"https://openalex.org/F4320321885","display_name":"Science and Technology Commission of Shanghai Municipality","ror":"https://ror.org/03kt66j61"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":40,"referenced_works":["https://openalex.org/W1605674139","https://openalex.org/W1901083236","https://openalex.org/W1966733028","https://openalex.org/W1970806136","https://openalex.org/W1975918566","https://openalex.org/W1984996269","https://openalex.org/W1991670063","https://openalex.org/W1991735330","https://openalex.org/W2007643334","https://openalex.org/W2014512534","https://openalex.org/W2016301038","https://openalex.org/W2036916361","https://openalex.org/W2039559700","https://openalex.org/W2081624924","https://openalex.org/W2082568343","https://openalex.org/W2082597509","https://openalex.org/W2096050740","https://openalex.org/W2096889604","https://openalex.org/W2099279767","https://openalex.org/W2116043630","https://openalex.org/W2135429635","https://openalex.org/W2156667996","https://openalex.org/W2157690147","https://openalex.org/W2162709529","https://openalex.org/W2178304595","https://openalex.org/W2183814442","https://openalex.org/W2289333215","https://openalex.org/W3144939025","https://openalex.org/W3146960355","https://openalex.org/W3149545534","https://openalex.org/W4231450833","https://openalex.org/W4235985757","https://openalex.org/W4236432903","https://openalex.org/W4242565052","https://openalex.org/W4244379914","https://openalex.org/W4245115327","https://openalex.org/W6642820234","https://openalex.org/W6648559587","https://openalex.org/W6652275138","https://openalex.org/W6660155203"],"related_works":["https://openalex.org/W1972953980","https://openalex.org/W2050988079","https://openalex.org/W1513897901","https://openalex.org/W4294000495","https://openalex.org/W2027800187","https://openalex.org/W2205497670","https://openalex.org/W2073623973","https://openalex.org/W2162705472","https://openalex.org/W2072390380","https://openalex.org/W2027268352"],"abstract_inverted_index":{"Energy-efficiency":[0],"optimization":[1,70],"occupies":[2],"an":[3,57,94,173],"important":[4],"position":[5],"in":[6,39,78,105,120,150,165],"the":[7,21,36,46,72,85,117,151,159,183,190,195,201],"Internet":[8],"of":[9,119],"Things":[10],"application.":[11],"The":[12,136,177],"error-resilience":[13],"technique":[14],"has":[15],"begun":[16],"to":[17],"emerge":[18],"and":[19,23,44,53,100,108,146,193],"brought":[20],"performance":[22],"energy":[24,184],"benefits":[25],"as":[26,65],"a":[27,66,80,131,143,166],"new":[28],"vision":[29],"for":[30],"alternative":[31],"computing,":[32],"because":[33],"it":[34,83,141,164,181],"eliminates":[35],"overconstrained":[37],"margin":[38],"current":[40],"processor":[41,170],"design":[42,112,192,204],"flow":[43],"protects":[45],"system":[47,81,111],"from":[48],"process,":[49],"supply":[50],"voltage,":[51],"temperature,":[52],"aging":[54],"variations":[55],"through":[56],"error-resilient":[58,95],"mechanism":[59,75],"rather":[60],"than":[61],"expensive":[62],"guardbands.":[63],"However,":[64],"traditional":[67],"clock-tree":[68],"power":[69,197],"technique,":[71],"clock":[73,97,134],"gating":[74],"cannot":[76],"work":[77,148],"such":[79],"when":[82],"faces":[84],"timing":[86,122],"violation":[87],"problem.":[88],"In":[89],"this":[90],"paper,":[91],"we":[92],"propose":[93],"integrated":[96,133],"gate":[98],"(ERICG)":[99],"its":[101],"automatic":[102],"integration":[103],"methodology":[104],"error":[106],"detection":[107],"correction":[109],"(EDAC)":[110],"flow.":[113],"ERICG":[114],"can":[115,147],"provide":[116],"ability":[118],"situ":[121],"EDAC":[123,203],"with":[124,130,189],"only":[125],"four":[126],"additional":[127],"transistors":[128],"compared":[129,188],"conventional":[132,202],"gate.":[135],"SPICE":[137],"simulation":[138],"shows":[139,179],"that":[140,180],"is":[142],"metastable-hardened":[144],"cell":[145],"well":[149],"wide":[152],"voltage":[153],"operation":[154],"(0.5~":[155],"1.1":[156],"V)":[157],"including":[158],"near-threshold":[160],"region.":[161],"We":[162],"implement":[163],"commercial":[167],"C-SKY":[168],"CK802":[169],"based":[171],"on":[172],"SMIC":[174],"40-nm":[175],"technology.":[176],"result":[178],"improves":[182],"efficiency":[185],"by":[186,198],"68%":[187],"non-EDAC":[191],"lowers":[194],"total":[196],"28.72%":[199],"over":[200],"at":[205],"0.6":[206],"V.":[207]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2023,"cited_by_count":2},{"year":2021,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}