{"id":"https://openalex.org/W2558474427","doi":"https://doi.org/10.1109/tvlsi.2016.2625809","title":"On Microarchitectural Mechanisms for Cache Wearout Reduction","display_name":"On Microarchitectural Mechanisms for Cache Wearout Reduction","publication_year":2016,"publication_date":"2016-11-29","ids":{"openalex":"https://openalex.org/W2558474427","doi":"https://doi.org/10.1109/tvlsi.2016.2625809","mag":"2558474427"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2016.2625809","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2016.2625809","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref","datacite"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"http://hdl.handle.net/10251/152477","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5001423758","display_name":"Alejandro Valero","orcid":"https://orcid.org/0000-0002-0824-5833"},"institutions":[{"id":"https://openalex.org/I60053951","display_name":"Universitat Polit\u00e8cnica de Val\u00e8ncia","ror":"https://ror.org/01460j859","country_code":"ES","type":"education","lineage":["https://openalex.org/I60053951"]},{"id":"https://openalex.org/I255234318","display_name":"Universidad de Zaragoza","ror":"https://ror.org/012a91z28","country_code":"ES","type":"education","lineage":["https://openalex.org/I255234318"]}],"countries":["ES"],"is_corresponding":true,"raw_author_name":"Alejandro Valero","raw_affiliation_strings":["Department of Computer Engineering, Universitat Polit\u00e8cnica de Val\u00e8ncia, Val\u00e8ncia, Spain","Department of Computer and Systems Engineering, University of Zaragoza, Zaragoza, Spain"],"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, Universitat Polit\u00e8cnica de Val\u00e8ncia, Val\u00e8ncia, Spain","institution_ids":["https://openalex.org/I60053951"]},{"raw_affiliation_string":"Department of Computer and Systems Engineering, University of Zaragoza, Zaragoza, Spain","institution_ids":["https://openalex.org/I255234318"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5056811144","display_name":"Negar Miralaei","orcid":null},"institutions":[{"id":"https://openalex.org/I241749","display_name":"University of Cambridge","ror":"https://ror.org/013meh722","country_code":"GB","type":"education","lineage":["https://openalex.org/I241749"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Negar Miralaei","raw_affiliation_strings":["University of Cambridge, Cambridge CB3 0FD, U.K"],"affiliations":[{"raw_affiliation_string":"University of Cambridge, Cambridge CB3 0FD, U.K","institution_ids":["https://openalex.org/I241749"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5013237315","display_name":"Salvador Petit","orcid":"https://orcid.org/0000-0003-2426-4134"},"institutions":[{"id":"https://openalex.org/I60053951","display_name":"Universitat Polit\u00e8cnica de Val\u00e8ncia","ror":"https://ror.org/01460j859","country_code":"ES","type":"education","lineage":["https://openalex.org/I60053951"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Salvador Petit","raw_affiliation_strings":["Department of Computer Engineering, Universitat Polit\u00e8cnica de Val\u00e8ncia, Val\u00e8ncia, Spain"],"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, Universitat Polit\u00e8cnica de Val\u00e8ncia, Val\u00e8ncia, Spain","institution_ids":["https://openalex.org/I60053951"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5044390347","display_name":"Julio Sahuquillo","orcid":"https://orcid.org/0000-0001-8630-4846"},"institutions":[{"id":"https://openalex.org/I60053951","display_name":"Universitat Polit\u00e8cnica de Val\u00e8ncia","ror":"https://ror.org/01460j859","country_code":"ES","type":"education","lineage":["https://openalex.org/I60053951"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Julio Sahuquillo","raw_affiliation_strings":["Department of Computer Engineering, Universitat Polit\u00e8cnica de Val\u00e8ncia, Val\u00e8ncia, Spain"],"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, Universitat Polit\u00e8cnica de Val\u00e8ncia, Val\u00e8ncia, Spain","institution_ids":["https://openalex.org/I60053951"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5047443783","display_name":"Timothy M. Jones","orcid":"https://orcid.org/0000-0002-4114-7661"},"institutions":[{"id":"https://openalex.org/I241749","display_name":"University of Cambridge","ror":"https://ror.org/013meh722","country_code":"GB","type":"education","lineage":["https://openalex.org/I241749"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Timothy M. Jones","raw_affiliation_strings":["Computer Laboratory, University of Cambridge, Cambridge CB3 0FD, UK"],"affiliations":[{"raw_affiliation_string":"Computer Laboratory, University of Cambridge, Cambridge CB3 0FD, UK","institution_ids":["https://openalex.org/I241749"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5001423758"],"corresponding_institution_ids":["https://openalex.org/I255234318","https://openalex.org/I60053951"],"apc_list":null,"apc_paid":null,"fwci":2.252,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":{"value":0.87911381,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":"25","issue":"3","first_page":"857","last_page":"871"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9972000122070312,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9950000047683716,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.7056745290756226},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6038563251495361},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.5807591676712036},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5312986373901367},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.07655614614486694}],"concepts":[{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.7056745290756226},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6038563251495361},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.5807591676712036},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5312986373901367},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.07655614614486694},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":4,"locations":[{"id":"doi:10.1109/tvlsi.2016.2625809","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2016.2625809","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},{"id":"pmh:oai:riunet.upv.es:10251/152477","is_oa":true,"landing_page_url":"http://hdl.handle.net/10251/152477","pdf_url":null,"source":{"id":"https://openalex.org/S4306401500","display_name":"RiuNet (Politechnical University of Valencia)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I60053951","host_organization_name":"Universitat Polit\u00e8cnica de Val\u00e8ncia","host_organization_lineage":["https://openalex.org/I60053951"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/article"},{"id":"pmh:oai:www.repository.cam.ac.uk:1810/261910","is_oa":false,"landing_page_url":"https://www.repository.cam.ac.uk/handle/1810/261910","pdf_url":null,"source":{"id":"https://openalex.org/S4306401777","display_name":"Apollo (University of Cambridge)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I241749","host_organization_name":"University of Cambridge","host_organization_lineage":["https://openalex.org/I241749"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Article"},{"id":"doi:10.17863/cam.7147","is_oa":true,"landing_page_url":"https://doi.org/10.17863/cam.7147","pdf_url":null,"source":{"id":"https://openalex.org/S7407050737","display_name":"Apollo","issn_l":null,"issn":[],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":null,"raw_source_name":null,"raw_type":"article-journal"}],"best_oa_location":{"id":"pmh:oai:riunet.upv.es:10251/152477","is_oa":true,"landing_page_url":"http://hdl.handle.net/10251/152477","pdf_url":null,"source":{"id":"https://openalex.org/S4306401500","display_name":"RiuNet (Politechnical University of Valencia)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I60053951","host_organization_name":"Universitat Polit\u00e8cnica de Val\u00e8ncia","host_organization_lineage":["https://openalex.org/I60053951"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/article"},"sustainable_development_goals":[{"score":0.5099999904632568,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[{"id":"https://openalex.org/G1258440726","display_name":null,"funder_award_id":"(MINECO","funder_id":"https://openalex.org/F4320321837","funder_display_name":"Ministerio de Econom\u00eda y Competitividad"},{"id":"https://openalex.org/G1934935867","display_name":null,"funder_award_id":"Engineering and Physical Sciences R","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"},{"id":"https://openalex.org/G3661743248","display_name":null,"funder_award_id":"EP/K026399/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"},{"id":"https://openalex.org/G4531677044","display_name":null,"funder_award_id":"grant","funder_id":"https://openalex.org/F4320321837","funder_display_name":"Ministerio de Econom\u00eda y Competitividad"},{"id":"https://openalex.org/G4628939008","display_name":"M3: Managing Many-Cores for the Masses","funder_award_id":"EP/K026399/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"},{"id":"https://openalex.org/G4985643425","display_name":"DOME: Delaying and Overcoming Microprocessor Errors","funder_award_id":"EP/J016284/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"},{"id":"https://openalex.org/G5376194459","display_name":null,"funder_award_id":"TIN2015-66972-C5-1-R","funder_id":"https://openalex.org/F4320321837","funder_display_name":"Ministerio de Econom\u00eda y Competitividad"},{"id":"https://openalex.org/G7609657460","display_name":null,"funder_award_id":"EP/J016284/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"}],"funders":[{"id":"https://openalex.org/F4320321837","display_name":"Ministerio de Econom\u00eda y Competitividad","ror":"https://ror.org/034900433"},{"id":"https://openalex.org/F4320334627","display_name":"Engineering and Physical Sciences Research Council","ror":"https://ror.org/0439y7842"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":39,"referenced_works":["https://openalex.org/W1996086722","https://openalex.org/W2022628721","https://openalex.org/W2041527398","https://openalex.org/W2048816638","https://openalex.org/W2056378733","https://openalex.org/W2057925451","https://openalex.org/W2088642150","https://openalex.org/W2088925784","https://openalex.org/W2089307123","https://openalex.org/W2094643138","https://openalex.org/W2099746875","https://openalex.org/W2103884786","https://openalex.org/W2104114347","https://openalex.org/W2106119416","https://openalex.org/W2108957996","https://openalex.org/W2110999128","https://openalex.org/W2115016937","https://openalex.org/W2122757690","https://openalex.org/W2129817078","https://openalex.org/W2141490184","https://openalex.org/W2154451732","https://openalex.org/W2155105016","https://openalex.org/W2158520623","https://openalex.org/W2161311133","https://openalex.org/W2162752393","https://openalex.org/W2171904653","https://openalex.org/W2224475358","https://openalex.org/W3145727536","https://openalex.org/W3148441651","https://openalex.org/W3161779574","https://openalex.org/W4235106764","https://openalex.org/W4235696082","https://openalex.org/W4240146668","https://openalex.org/W4241505725","https://openalex.org/W4253202538","https://openalex.org/W6664196189","https://openalex.org/W6675651536","https://openalex.org/W6679030935","https://openalex.org/W6680597583"],"related_works":["https://openalex.org/W4391375266","https://openalex.org/W2748952813","https://openalex.org/W2390279801","https://openalex.org/W2358668433","https://openalex.org/W4396701345","https://openalex.org/W2376932109","https://openalex.org/W2001405890","https://openalex.org/W4396696052","https://openalex.org/W2382290278","https://openalex.org/W4395014643"],"abstract_inverted_index":{"Hot":[0],"carrier":[1],"injection":[2],"(HCI)":[3],"and":[4,35,53,104,124,215],"bias":[5],"temperature":[6],"instability":[7],"(BTI)":[8],"are":[9,78,95,100,106,143,225],"two":[10],"of":[11,25,61,73,90,130,140,149,191,202,209,219],"the":[12,23,59,65,87,127,138,162,170,207,217,228,240,252],"main":[13],"deleterious":[14],"effects":[15,119],"that":[16,137,166,205,221,239],"increase":[17],"a":[18,26,62,146,176,183,188,200],"transistor's":[19],"threshold":[20,241],"voltage":[21,29,242],"over":[22],"lifetime":[24],"microprocessor.":[27],"This":[28,109],"degradation":[30,243],"causes":[31],"slower":[32],"transistor":[33,63,117],"switching":[34,231],"eventually":[36],"can":[37],"result":[38,60],"in":[39,81,126,145,175,227],"faulty":[40],"operation.":[41],"HCI":[42,123],"manifests":[43],"itself":[44],"when":[45],"transistors":[46,83],"switch":[47],"from":[48,246],"logic":[49,67,167,185,222],"\u201c0\u201d":[50,168,223],"to":[51,85,102,115,248],"\u201c1\u201d":[52],"vice":[54],"versa,":[55],"whereas":[56],"BTI":[57,125],"is":[58,169],"maintaining":[64],"same":[66],"value":[68,174,186],"for":[69,187],"an":[70],"extended":[71],"period":[72],"time.":[74,192],"These":[75],"failure":[76],"mechanisms":[77],"especially":[79],"acute":[80],"those":[82],"used":[84],"implement":[86],"SRAM":[88],"cells":[89,181,214,229],"first-level":[91],"(L1)":[92],"caches,":[93],"which":[94,180],"frequently":[96,172],"accessed,":[97],"so":[98],"they":[99,105],"critical":[101],"performance,":[103],"continuously":[107],"aging.":[108],"paper":[110,198],"focuses":[111],"on":[112,194,251],"microarchitectural":[113],"solutions":[114],"reduce":[116,216],"aging":[118],"induced":[120],"by":[121,178,230],"both":[122],"data":[128,132,154,234],"array":[129],"L1":[131],"caches.":[133],"First,":[134],"we":[135,158],"show":[136,238],"majority":[139],"cell":[141],"flips":[142,210],"concentrated":[144],"small":[147],"number":[148,201,208],"specific":[150,233],"bits":[151],"within":[152],"each":[153],"word.":[155],"In":[156],"addition,":[157],"also":[159],"build":[160],"upon":[161],"previous":[163],"studies,":[164],"showing":[165],"most":[171],"written":[173],"cache":[177],"identifying":[179],"hold":[182],"given":[184],"significant":[189],"amount":[190,218],"Based":[193],"these":[195],"observations,":[196],"this":[197],"introduces":[199],"architectural":[203],"techniques":[204],"spread":[206],"evenly":[211],"across":[212],"memory":[213],"time":[220],"values":[224],"stored":[226],"OFF":[232],"bytes.":[235],"Experimental":[236],"results":[237],"savings":[244],"range":[245],"21.8%":[247],"44.3%":[249],"depending":[250],"application.":[253]},"counts_by_year":[{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":4},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":2}],"updated_date":"2026-03-14T08:43:22.919905","created_date":"2016-12-08T00:00:00"}
