{"id":"https://openalex.org/W2559852827","doi":"https://doi.org/10.1109/tvlsi.2016.2615306","title":"An Analog CVNS-Based Sigmoid Neuron for Precise Neurochips","display_name":"An Analog CVNS-Based Sigmoid Neuron for Precise Neurochips","publication_year":2016,"publication_date":"2016-12-07","ids":{"openalex":"https://openalex.org/W2559852827","doi":"https://doi.org/10.1109/tvlsi.2016.2615306","mag":"2559852827"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2016.2615306","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2016.2615306","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5088940027","display_name":"Babak Zamanlooy","orcid":"https://orcid.org/0000-0001-9608-5229"},"institutions":[{"id":"https://openalex.org/I74413500","display_name":"University of Windsor","ror":"https://ror.org/01gw3d370","country_code":"CA","type":"education","lineage":["https://openalex.org/I74413500"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Babak Zamanlooy","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Windsor, Windsor, ON, Canada"],"raw_orcid":"https://orcid.org/0000-0001-9608-5229","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Windsor, Windsor, ON, Canada","institution_ids":["https://openalex.org/I74413500"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5042170452","display_name":"Mitra Mirhassani","orcid":"https://orcid.org/0000-0001-8512-6427"},"institutions":[{"id":"https://openalex.org/I74413500","display_name":"University of Windsor","ror":"https://ror.org/01gw3d370","country_code":"CA","type":"education","lineage":["https://openalex.org/I74413500"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Mitra Mirhassani","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Windsor, Windsor, ON, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Windsor, Windsor, ON, Canada","institution_ids":["https://openalex.org/I74413500"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I74413500"],"apc_list":null,"apc_paid":null,"fwci":1.3647,"has_fulltext":false,"cited_by_count":25,"citation_normalized_percentile":{"value":0.8119359,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":"25","issue":"3","first_page":"894","last_page":"906"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10320","display_name":"Neural Networks and Applications","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/sigmoid-function","display_name":"Sigmoid function","score":0.8402751088142395},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5210044384002686},{"id":"https://openalex.org/keywords/artificial-neural-network","display_name":"Artificial neural network","score":0.4091343581676483},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.33329105377197266},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.22520306706428528},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.10963016748428345}],"concepts":[{"id":"https://openalex.org/C81388566","wikidata":"https://www.wikidata.org/wiki/Q526668","display_name":"Sigmoid function","level":3,"score":0.8402751088142395},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5210044384002686},{"id":"https://openalex.org/C50644808","wikidata":"https://www.wikidata.org/wiki/Q192776","display_name":"Artificial neural network","level":2,"score":0.4091343581676483},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.33329105377197266},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.22520306706428528},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.10963016748428345}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2016.2615306","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2016.2615306","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.7900000214576721,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320310709","display_name":"CMC Microsystems","ror":"https://ror.org/03k70ea39"},{"id":"https://openalex.org/F4320334593","display_name":"Natural Sciences and Engineering Research Council of Canada","ror":"https://ror.org/01h531d29"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":31,"referenced_works":["https://openalex.org/W1483062991","https://openalex.org/W1896727441","https://openalex.org/W1966782580","https://openalex.org/W1973695593","https://openalex.org/W1978262091","https://openalex.org/W2000956074","https://openalex.org/W2012840657","https://openalex.org/W2023745373","https://openalex.org/W2025922849","https://openalex.org/W2044406471","https://openalex.org/W2044688329","https://openalex.org/W2054507989","https://openalex.org/W2067184091","https://openalex.org/W2070804437","https://openalex.org/W2071654592","https://openalex.org/W2094621017","https://openalex.org/W2096263144","https://openalex.org/W2108077305","https://openalex.org/W2112016429","https://openalex.org/W2128140661","https://openalex.org/W2128273462","https://openalex.org/W2130017646","https://openalex.org/W2134438536","https://openalex.org/W2135407475","https://openalex.org/W2150380720","https://openalex.org/W2162851503","https://openalex.org/W2167425979","https://openalex.org/W2169621283","https://openalex.org/W2510605586","https://openalex.org/W6682044802","https://openalex.org/W6725748452"],"related_works":["https://openalex.org/W2748952813","https://openalex.org/W4385957115","https://openalex.org/W2061372042","https://openalex.org/W3047779762","https://openalex.org/W1520030019","https://openalex.org/W2071654592","https://openalex.org/W3104477175","https://openalex.org/W2088157920","https://openalex.org/W4283785902","https://openalex.org/W3170224572"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"the":[3,18,25,30,37,65,73,81,84,109,144],"design":[4],"and":[5,97,131,147],"implementation":[6,96,107,118],"of":[7,17,54,64,108,128],"an":[8,93],"analog":[9,31,47,62],"sigmoid":[10,56],"neuron":[11,20,35,57,90,110,136],"is":[12,21,79,98,111],"presented.":[13],"The":[14,33,87,105,117,134],"activation":[15],"function":[16],"proposed":[19,34,88,135],"implemented":[22],"based":[23],"on":[24],"piecewise":[26],"linear":[27],"approximation":[28,77],"in":[29,44,92,126],"domain.":[32],"provides":[36],"required":[38],"accuracy":[39],"that":[40],"cannot":[41],"be":[42],"achieved":[43],"general":[45],"by":[46],"neural":[48],"network":[49],"implementations.":[50],"General":[51],"digital":[52,85],"outputs":[53],"a":[55],"are":[58],"replaced":[59],"with":[60,102,122,143],"fewer":[61],"digits":[63],"continuous":[66],"valued":[67],"number":[68],"system":[69],"(CVNS),":[70],"while":[71],"at":[72],"same":[74,82],"time":[75],"maximum":[76],"error":[78],"kept":[80],"as":[83],"architectures.":[86],"CVNS":[89],"resulted":[91],"optimal":[94],"ASIC":[95],"suitable":[99],"for":[100],"neurochips":[101],"on-chip":[103],"learning.":[104],"VLSI":[106],"carried":[112],"out":[113],"using":[114],"current-mode":[115],"circuits.":[116],"results":[119],"compare":[120],"favorably":[121],"previously":[123],"developed":[124],"structures":[125],"terms":[127],"area,":[129],"delay,":[130],"power":[132,153],"consumption.":[133],"structure":[137],"occupies":[138],"28%":[139],"less":[140],"area":[141],"compared":[142],"state-of-the-art":[145],"methods":[146],"it":[148],"has":[149],"two":[150],"times":[151],"lower":[152],"\u00d7":[154],"delay.":[155]},"counts_by_year":[{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":3},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":7},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":4},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
