{"id":"https://openalex.org/W2545422235","doi":"https://doi.org/10.1109/tvlsi.2016.2614695","title":"A 0.1\u20132-GHz Quadrature Correction Loop for Digital Multiphase Clock Generation Circuits in 130-nm CMOS","display_name":"A 0.1\u20132-GHz Quadrature Correction Loop for Digital Multiphase Clock Generation Circuits in 130-nm CMOS","publication_year":2016,"publication_date":"2016-10-28","ids":{"openalex":"https://openalex.org/W2545422235","doi":"https://doi.org/10.1109/tvlsi.2016.2614695","mag":"2545422235"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2016.2614695","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2016.2614695","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5073557770","display_name":"Immanuel Raja","orcid":"https://orcid.org/0000-0002-2960-3644"},"institutions":[{"id":"https://openalex.org/I59270414","display_name":"Indian Institute of Science Bangalore","ror":"https://ror.org/04dese585","country_code":"IN","type":"education","lineage":["https://openalex.org/I59270414"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Immanuel Raja","raw_affiliation_strings":["Department of Electrical Communication Engineering, Indian Institute of Science, Bengaluru, India","Department of Electrical Communication Engineering Indian Institute of Science Bengaluru India"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Communication Engineering, Indian Institute of Science, Bengaluru, India","institution_ids":["https://openalex.org/I59270414"]},{"raw_affiliation_string":"Department of Electrical Communication Engineering Indian Institute of Science Bengaluru India","institution_ids":["https://openalex.org/I59270414"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5006642594","display_name":"Vishal Khatri","orcid":"https://orcid.org/0000-0001-9199-8598"},"institutions":[{"id":"https://openalex.org/I59270414","display_name":"Indian Institute of Science Bangalore","ror":"https://ror.org/04dese585","country_code":"IN","type":"education","lineage":["https://openalex.org/I59270414"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Vishal Khatri","raw_affiliation_strings":["Department of Electrical Communication Engineering, Indian Institute of Science, Bengaluru, India","Department of Electrical Communication Engineering Indian Institute of Science Bengaluru India"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Communication Engineering, Indian Institute of Science, Bengaluru, India","institution_ids":["https://openalex.org/I59270414"]},{"raw_affiliation_string":"Department of Electrical Communication Engineering Indian Institute of Science Bengaluru India","institution_ids":["https://openalex.org/I59270414"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5055412219","display_name":"Zaira Zahir","orcid":"https://orcid.org/0000-0003-0847-4369"},"institutions":[{"id":"https://openalex.org/I59270414","display_name":"Indian Institute of Science Bangalore","ror":"https://ror.org/04dese585","country_code":"IN","type":"education","lineage":["https://openalex.org/I59270414"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Zaira Zahir","raw_affiliation_strings":["Department of Electrical Communication Engineering, Indian Institute of Science, Bengaluru, India","Department of Electrical Communication Engineering Indian Institute of Science Bengaluru India"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Communication Engineering, Indian Institute of Science, Bengaluru, India","institution_ids":["https://openalex.org/I59270414"]},{"raw_affiliation_string":"Department of Electrical Communication Engineering Indian Institute of Science Bengaluru India","institution_ids":["https://openalex.org/I59270414"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5102785192","display_name":"Gaurab Banerjee","orcid":"https://orcid.org/0000-0003-4858-7683"},"institutions":[{"id":"https://openalex.org/I59270414","display_name":"Indian Institute of Science Bangalore","ror":"https://ror.org/04dese585","country_code":"IN","type":"education","lineage":["https://openalex.org/I59270414"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Gaurab Banerjee","raw_affiliation_strings":["Department of Electrical Communication Engineering, Indian Institute of Science, Bengaluru, India","Department of Electrical Communication Engineering Indian Institute of Science Bengaluru India"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Communication Engineering, Indian Institute of Science, Bengaluru, India","institution_ids":["https://openalex.org/I59270414"]},{"raw_affiliation_string":"Department of Electrical Communication Engineering Indian Institute of Science Bengaluru India","institution_ids":["https://openalex.org/I59270414"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5073557770"],"corresponding_institution_ids":["https://openalex.org/I59270414"],"apc_list":null,"apc_paid":null,"fwci":1.1154,"has_fulltext":false,"cited_by_count":13,"citation_normalized_percentile":{"value":0.81064301,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":"25","issue":"3","first_page":"1044","last_page":"1053"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7419240474700928},{"id":"https://openalex.org/keywords/quadrature","display_name":"Quadrature (astronomy)","score":0.658860445022583},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5725960731506348},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5401268601417542},{"id":"https://openalex.org/keywords/duty-cycle","display_name":"Duty cycle","score":0.4483019709587097},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.44215846061706543},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.4107837677001953},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.38836950063705444},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.3408362865447998},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3217560946941376},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.31168195605278015},{"id":"https://openalex.org/keywords/phase-noise","display_name":"Phase noise","score":0.13443195819854736}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7419240474700928},{"id":"https://openalex.org/C62869609","wikidata":"https://www.wikidata.org/wiki/Q28137","display_name":"Quadrature (astronomy)","level":2,"score":0.658860445022583},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5725960731506348},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5401268601417542},{"id":"https://openalex.org/C199822604","wikidata":"https://www.wikidata.org/wiki/Q557120","display_name":"Duty cycle","level":3,"score":0.4483019709587097},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.44215846061706543},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.4107837677001953},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.38836950063705444},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.3408362865447998},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3217560946941376},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.31168195605278015},{"id":"https://openalex.org/C89631360","wikidata":"https://www.wikidata.org/wiki/Q1428766","display_name":"Phase noise","level":2,"score":0.13443195819854736}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/tvlsi.2016.2614695","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2016.2614695","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},{"id":"pmh:oai:eprints.iisc.ac.in:56424","is_oa":false,"landing_page_url":null,"pdf_url":null,"source":{"id":"https://openalex.org/S4377196309","display_name":"NOT FOUND REPOSITORY (Indian Institute of Science Bangalore)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I59270414","host_organization_name":"Indian Institute of Science Bangalore","host_organization_lineage":["https://openalex.org/I59270414"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"acceptedVersion","is_accepted":true,"is_published":false,"raw_source_name":"","raw_type":"Journal Article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.800000011920929,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W2022601992","https://openalex.org/W2056358418","https://openalex.org/W2060005501","https://openalex.org/W2096516547","https://openalex.org/W2096867652","https://openalex.org/W2099123495","https://openalex.org/W2103792596","https://openalex.org/W2110848220","https://openalex.org/W2124602441","https://openalex.org/W2131845126","https://openalex.org/W2135441328","https://openalex.org/W2141065738","https://openalex.org/W2164188348","https://openalex.org/W2323422058","https://openalex.org/W2340566934","https://openalex.org/W6665144040","https://openalex.org/W6675189111"],"related_works":["https://openalex.org/W1576949837","https://openalex.org/W4360861688","https://openalex.org/W3134930219","https://openalex.org/W984417604","https://openalex.org/W2967785526","https://openalex.org/W2065391525","https://openalex.org/W4318711045","https://openalex.org/W2151251192","https://openalex.org/W2389800961","https://openalex.org/W1995389502"],"abstract_inverted_index":{"A":[0],"100-MHz-2-GHz":[1],"closed-loop":[2],"analog":[3],"in-phase/":[4],"quadrature":[5,23,86],"correction":[6],"circuit":[7,15,27,60,95],"for":[8,22,102],"digital":[9],"clocks":[10],"is":[11],"presented.":[12],"The":[13,26,59,76,93],"proposed":[14,94],"consists":[16],"of":[17,72,78],"a":[18,34,52],"phase-locked":[19],"looptype":[20],"architecture":[21],"error":[24,31],"correction.":[25],"corrects":[28],"the":[29,104],"phase":[30],"to":[32,37,41],"within":[33,42],"1.5\u00b0":[35],"up":[36],"1":[38],"GHz":[39],"and":[40],"3\u00b0":[43],"at":[44,56],"2":[45,57],"GHz.":[46,58],"It":[47],"consumes":[48],"5.4":[49],"mA":[50],"from":[51],"1.2":[53],"V":[54],"supply":[55],"was":[61,96],"designed":[62],"in":[63,98],"UMC":[64],"0.13-\u03bcm":[65],"mixed-mode":[66],"CMOS":[67],"with":[68],"an":[69],"active":[70],"area":[71],"102":[73],"\u03bcm\u00d795":[74],"\u03bcm.":[75],"impact":[77],"duty":[79],"cycle":[80],"distortion":[81],"has":[82,106],"been":[83,91,107],"analyzed.":[84],"High-frequency":[85],"measurement":[87],"related":[88],"issues":[89],"have":[90],"discussed.":[92],"used":[97],"two":[99],"different":[100],"applications":[101],"which":[103],"functionality":[105],"verified.":[108]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":4},{"year":2018,"cited_by_count":2}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}