{"id":"https://openalex.org/W2505495620","doi":"https://doi.org/10.1109/tvlsi.2016.2580713","title":"A 10 Gbits/s/pin DFE-Less Graphics DRAM Interface With Adaptive-Bandwidth PLL for Avoiding Noise Interference and CIJ Reduction Technique","display_name":"A 10 Gbits/s/pin DFE-Less Graphics DRAM Interface With Adaptive-Bandwidth PLL for Avoiding Noise Interference and CIJ Reduction Technique","publication_year":2016,"publication_date":"2016-07-20","ids":{"openalex":"https://openalex.org/W2505495620","doi":"https://doi.org/10.1109/tvlsi.2016.2580713","mag":"2505495620"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2016.2580713","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2016.2580713","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5025679671","display_name":"Junyoung Song","orcid":"https://orcid.org/0000-0002-7994-7234"},"institutions":[{"id":"https://openalex.org/I197347611","display_name":"Korea University","ror":"https://ror.org/047dqcg40","country_code":"KR","type":"education","lineage":["https://openalex.org/I197347611"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Junyoung Song","raw_affiliation_strings":["Department of Electronics and Electrical Engineering, Korea University, Seoul, South Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics and Electrical Engineering, Korea University, Seoul, South Korea","institution_ids":["https://openalex.org/I197347611"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100334311","display_name":"Hyun-Woo Lee","orcid":"https://orcid.org/0000-0001-9484-8456"},"institutions":[{"id":"https://openalex.org/I134353371","display_name":"SK Group (South Korea)","ror":"https://ror.org/03696td91","country_code":"KR","type":"company","lineage":["https://openalex.org/I134353371"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Hyun-Woo Lee","raw_affiliation_strings":["SK Hynix semiconductor Inc., Icheon, South Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"SK Hynix semiconductor Inc., Icheon, South Korea","institution_ids":["https://openalex.org/I134353371"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111840518","display_name":"Sewook Hwang","orcid":null},"institutions":[{"id":"https://openalex.org/I197347611","display_name":"Korea University","ror":"https://ror.org/047dqcg40","country_code":"KR","type":"education","lineage":["https://openalex.org/I197347611"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Sewook Hwang","raw_affiliation_strings":["Department of Electronics and Electrical Engineering, Korea University, Seoul, South Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics and Electrical Engineering, Korea University, Seoul, South Korea","institution_ids":["https://openalex.org/I197347611"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100777100","display_name":"Chulwoo Kim","orcid":"https://orcid.org/0000-0003-4379-7905"},"institutions":[{"id":"https://openalex.org/I197347611","display_name":"Korea University","ror":"https://ror.org/047dqcg40","country_code":"KR","type":"education","lineage":["https://openalex.org/I197347611"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Chulwoo Kim","raw_affiliation_strings":["Department of Electronics and Electrical Engineering, Korea University, Seoul, South Korea"],"raw_orcid":"https://orcid.org/0000-0003-4379-7905","affiliations":[{"raw_affiliation_string":"Department of Electronics and Electrical Engineering, Korea University, Seoul, South Korea","institution_ids":["https://openalex.org/I197347611"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":{"value":2645,"currency":"USD","value_usd":2645},"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.05801134,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"25","issue":"1","first_page":"344","last_page":"353"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9965999722480774,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.8903731107711792},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.7532278299331665},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6506389379501343},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6215700507164001},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5744728446006775},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.5625001788139343},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.5333390831947327},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.43152642250061035},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.42555370926856995},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.24135646224021912},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08775407075881958}],"concepts":[{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.8903731107711792},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.7532278299331665},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6506389379501343},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6215700507164001},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5744728446006775},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.5625001788139343},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.5333390831947327},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.43152642250061035},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.42555370926856995},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.24135646224021912},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08775407075881958}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2016.2580713","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2016.2580713","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8700000047683716,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[{"id":"https://openalex.org/G294724227","display_name":null,"funder_award_id":"NRF-2013R1A2A1A03070988","funder_id":"https://openalex.org/F4320322120","funder_display_name":"National Research Foundation of Korea"}],"funders":[{"id":"https://openalex.org/F4320322120","display_name":"National Research Foundation of Korea","ror":"https://ror.org/013aysd81"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":26,"referenced_works":["https://openalex.org/W1607361739","https://openalex.org/W1964108470","https://openalex.org/W1979377088","https://openalex.org/W1985419217","https://openalex.org/W2015184411","https://openalex.org/W2039706313","https://openalex.org/W2062952706","https://openalex.org/W2080728704","https://openalex.org/W2089757817","https://openalex.org/W2103011017","https://openalex.org/W2104543397","https://openalex.org/W2107304970","https://openalex.org/W2108647531","https://openalex.org/W2126052777","https://openalex.org/W2126887978","https://openalex.org/W2150616627","https://openalex.org/W2151755625","https://openalex.org/W2169980127","https://openalex.org/W2174378327","https://openalex.org/W2175184221","https://openalex.org/W4255435342","https://openalex.org/W6646499804","https://openalex.org/W6672938105","https://openalex.org/W6678875593","https://openalex.org/W6682409399","https://openalex.org/W6685038751"],"related_works":["https://openalex.org/W2121182846","https://openalex.org/W2315668284","https://openalex.org/W2155789024","https://openalex.org/W3213608175","https://openalex.org/W3117675750","https://openalex.org/W2141743053","https://openalex.org/W2109491806","https://openalex.org/W2094329012","https://openalex.org/W1994021281","https://openalex.org/W2139484866"],"abstract_inverted_index":{"A":[0,24],"10":[1,100],"Gbits/s/pin":[2,101],"graphics":[3],"DRAM":[4],"interface":[5],"is":[6,51],"developed":[7],"in":[8,20,92],"65-nm":[9],"CMOS":[10],"technology.":[11],"Several":[12],"design":[13],"techniques":[14],"are":[15,90,124],"proposed":[16],"for":[17,35,83],"high-speed":[18,30],"operation":[19],"a":[21,36,104],"noisy":[22],"environment.":[23],"fast":[25],"precharging":[26],"data":[27,45,105],"sampler":[28],"guarantees":[29],"sampling":[31,46],"without":[32],"the":[33,44,48,55,60,74,79,84,112,120],"need":[34],"decision":[37],"feedback":[38],"equalizer.":[39],"In":[40],"order":[41],"to":[42,65],"increase":[43],"margin,":[47],"PLL":[49],"bandwidth":[50],"optimized":[52],"depending":[53],"on":[54],"system":[56],"noises,":[57],"which":[58],"reduces":[59],"clock":[61],"jitter":[62,69,76],"by":[63,77],"up":[64],"55.1%.":[66],"The":[67,116],"crosstalk-induced":[68],"(CIJ)":[70],"reduction":[71,114],"technique":[72],"suppresses":[73],"DQs":[75],"employing":[78],"suggested":[80],"training":[81],"sequence":[82],"GDDR5":[85],"interface.":[86],"Pre-":[87],"and":[88,102,122,126],"de-emphasis":[89],"merged":[91],"one":[93],"auxiliary":[94],"driver.":[95],"This":[96],"chip":[97],"operates":[98],"at":[99],"exhibits":[103],"eye":[106],"opening":[107],"of":[108,119],"0.78":[109],"UI":[110],"with":[111],"CIJ":[113],"technique.":[115],"power":[117],"consumptions":[118],"TX":[121],"RX":[123],"8.28":[125],"5.5":[127],"pJ/b/channel,":[128],"respectively.":[129]},"counts_by_year":[],"updated_date":"2026-08-21T09:56:20.448147","created_date":"2025-10-10T00:00:00"}