{"id":"https://openalex.org/W2473691961","doi":"https://doi.org/10.1109/tvlsi.2016.2578933","title":"ENFIRE: A Spatio-Temporal Fine-Grained Reconfigurable Hardware","display_name":"ENFIRE: A Spatio-Temporal Fine-Grained Reconfigurable Hardware","publication_year":2016,"publication_date":"2016-06-24","ids":{"openalex":"https://openalex.org/W2473691961","doi":"https://doi.org/10.1109/tvlsi.2016.2578933","mag":"2473691961"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2016.2578933","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2016.2578933","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5087800100","display_name":"Wenchao Qian","orcid":"https://orcid.org/0000-0002-7288-498X"},"institutions":[{"id":"https://openalex.org/I32923980","display_name":"Xilinx (United States)","ror":"https://ror.org/01rb7bk56","country_code":"US","type":"company","lineage":["https://openalex.org/I32923980"]},{"id":"https://openalex.org/I58956616","display_name":"Case Western Reserve University","ror":"https://ror.org/051fd9666","country_code":"US","type":"education","lineage":["https://openalex.org/I58956616"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Wenchao Qian","raw_affiliation_strings":["Department of Electrical Engineering and Computer Science, Case Western Reserve University, Cleveland, OH, USA","Xilinx Inc., San Jose, CA, USA"],"raw_orcid":"https://orcid.org/0000-0002-7288-498X","affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering and Computer Science, Case Western Reserve University, Cleveland, OH, USA","institution_ids":["https://openalex.org/I58956616"]},{"raw_affiliation_string":"Xilinx Inc., San Jose, CA, USA","institution_ids":["https://openalex.org/I32923980"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5053294874","display_name":"Christopher Babecki","orcid":"https://orcid.org/0000-0002-5253-0113"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Christopher Babecki","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5049193989","display_name":"Robert Karam","orcid":"https://orcid.org/0000-0002-2713-029X"},"institutions":[{"id":"https://openalex.org/I33213144","display_name":"University of Florida","ror":"https://ror.org/02y3ad647","country_code":"US","type":"education","lineage":["https://openalex.org/I33213144"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Robert Karam","raw_affiliation_strings":["University of Florida, Gainesville, FL, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Florida, Gainesville, FL, USA","institution_ids":["https://openalex.org/I33213144"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100619719","display_name":"Somnath Paul","orcid":"https://orcid.org/0000-0001-9908-669X"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Somnath Paul","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5039442844","display_name":"Swarup Bhunia","orcid":"https://orcid.org/0000-0001-6082-6961"},"institutions":[{"id":"https://openalex.org/I33213144","display_name":"University of Florida","ror":"https://ror.org/02y3ad647","country_code":"US","type":"education","lineage":["https://openalex.org/I33213144"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Swarup Bhunia","raw_affiliation_strings":["University of Florida, Gainesville, FL, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Florida, Gainesville, FL, USA","institution_ids":["https://openalex.org/I33213144"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.06468269,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"25","issue":"1","first_page":"177","last_page":"188"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7928678393363953},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7834281921386719},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.7189581394195557},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.66927170753479},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.569580078125},{"id":"https://openalex.org/keywords/efficient-energy-use","display_name":"Efficient energy use","score":0.5390138030052185},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5288074016571045},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4460412859916687},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4173493981361389},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3737209141254425},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.34784579277038574},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.09052354097366333}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7928678393363953},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7834281921386719},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.7189581394195557},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.66927170753479},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.569580078125},{"id":"https://openalex.org/C2742236","wikidata":"https://www.wikidata.org/wiki/Q924713","display_name":"Efficient energy use","level":2,"score":0.5390138030052185},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5288074016571045},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4460412859916687},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4173493981361389},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3737209141254425},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.34784579277038574},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.09052354097366333},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2016.2578933","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2016.2578933","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8999999761581421,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[{"id":"https://openalex.org/G5335343950","display_name":null,"funder_award_id":"2015-EP-2650","funder_id":"https://openalex.org/F4320306087","funder_display_name":"Semiconductor Research Corporation"}],"funders":[{"id":"https://openalex.org/F4320306087","display_name":"Semiconductor Research Corporation","ror":"https://ror.org/047z4n946"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":29,"referenced_works":["https://openalex.org/W1498249569","https://openalex.org/W1964761923","https://openalex.org/W1969802502","https://openalex.org/W1979667739","https://openalex.org/W2010739078","https://openalex.org/W2014208555","https://openalex.org/W2015558226","https://openalex.org/W2016889342","https://openalex.org/W2019053833","https://openalex.org/W2022738220","https://openalex.org/W2025787141","https://openalex.org/W2041871970","https://openalex.org/W2051535448","https://openalex.org/W2085651287","https://openalex.org/W2095595785","https://openalex.org/W2113289989","https://openalex.org/W2118216565","https://openalex.org/W2121903189","https://openalex.org/W2128239317","https://openalex.org/W2137570657","https://openalex.org/W2138815064","https://openalex.org/W2146185334","https://openalex.org/W2149513075","https://openalex.org/W2165099691","https://openalex.org/W2165432685","https://openalex.org/W4206412226","https://openalex.org/W4234479839","https://openalex.org/W6641528655","https://openalex.org/W6671447578"],"related_works":["https://openalex.org/W1612076744","https://openalex.org/W2126857316","https://openalex.org/W2129019972","https://openalex.org/W3164085601","https://openalex.org/W1522032972","https://openalex.org/W2139962137","https://openalex.org/W2113308450","https://openalex.org/W2340647897","https://openalex.org/W3139915793","https://openalex.org/W4200391368"],"abstract_inverted_index":{"Field":[0],"programmable":[1,30],"gate":[2],"arrays":[3,95],"(FPGAs)":[4],"are":[5,124,138],"well-established":[6],"as":[7,97,128],"fine-grained":[8,45],"reconfigurable":[9,82],"computing":[10,59,100,143],"platforms.":[11],"However,":[12],"FPGAs":[13],"demonstrate":[14],"poor":[15],"scalability":[16,88],"in":[17,49,62,179,182,186,190],"advanced":[18],"technology":[19],"nodes":[20],"due":[21],"to":[22,77,107,152],"the":[23,28,50,56,63,79,98,105,112,116,136,153,165],"large":[24],"negative":[25],"impact":[26],"of":[27,81,115,177],"elaborate":[29],"interconnects":[31],"(PIs).":[32],"The":[33],"need":[34],"for":[35],"such":[36],"vast":[37],"PIs":[38],"arises":[39],"from":[40],"two":[41],"key":[42],"factors:":[43],"1)":[44],"bit-level":[46,83],"data":[47,106],"manipulation":[48],"configurable":[51],"logic":[52],"blocks":[53],"and":[54,89,159,188,199],"2)":[55],"purely":[57],"spatial":[58,158],"model":[60],"followed":[61],"FPGAs.":[64],"In":[65],"this":[66],"paper,":[67],"we":[68],"propose":[69],"ENFIRE,":[70],"a":[71,131,194],"novel":[72],"memory-based":[73],"spatio-temporal":[74],"framework":[75,148],"designed":[76],"provide":[78],"flexibility":[80],"information":[84],"processing":[85],"while":[86,135],"improving":[87],"energy":[90,183,192,198],"efficiency.":[91],"Dense":[92],"2-D":[93],"memory":[94],"serve":[96],"main":[99],"elements":[101,123],"storing":[102],"not":[103],"only":[104],"be":[108],"processed":[109],"but":[110],"also":[111],"functional":[113],"behavior":[114],"application":[117,150],"mapped":[118],"into":[119],"lookup":[120],"tables.":[121],"Computing":[122],"spatially":[125],"distributed,":[126],"communicating":[127],"needed":[129],"over":[130],"hierarchical":[132],"bus":[133],"interconnect,":[134],"functions":[137],"evaluated":[139],"temporally":[140],"inside":[141],"each":[142],"element.":[144],"A":[145],"custom":[146],"software":[147],"facilitates":[149],"mapping":[151],"framework.":[154],"By":[155],"leveraging":[156],"both":[157],"temporal":[160],"computing,":[161],"ENFIRE":[162],"significantly":[163],"reduces":[164],"interconnect":[166],"overhead":[167],"when":[168],"compared":[169,202],"with":[170,203],"FPGA.":[171],"Simulation":[172],"results":[173],"show":[174],"an":[175],"improvement":[176],"7.6\u00d7":[178],"energy,":[180],"1.6\u00d7":[181],"efficiency,":[184,193],"1.1\u00d7":[185],"leakage,":[187],"5.3\u00d7":[189],"unified":[191],"metric":[195],"that":[196],"considers":[197],"area":[200],"together,":[201],"comparable":[204],"FPGA":[205],"implementations.":[206]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":2}],"updated_date":"2026-03-27T05:58:40.876381","created_date":"2025-10-10T00:00:00"}