{"id":"https://openalex.org/W2399857432","doi":"https://doi.org/10.1109/tvlsi.2016.2562361","title":"Floorplanning Automation for Partial-Reconfigurable FPGAs via Feasible Placements Generation","display_name":"Floorplanning Automation for Partial-Reconfigurable FPGAs via Feasible Placements Generation","publication_year":2016,"publication_date":"2016-05-25","ids":{"openalex":"https://openalex.org/W2399857432","doi":"https://doi.org/10.1109/tvlsi.2016.2562361","mag":"2399857432"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2016.2562361","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2016.2562361","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"http://hdl.handle.net/11311/1006255","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5008834768","display_name":"Marco Rabozzi","orcid":null},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Marco Rabozzi","raw_affiliation_strings":["Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano, Milan, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano, Milan, Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5086932958","display_name":"Gianluca Durelli","orcid":null},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Gianluca Carlo Durelli","raw_affiliation_strings":["Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano, Milan, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano, Milan, Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031451381","display_name":"Antonio Miele","orcid":"https://orcid.org/0000-0003-3197-0723"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Antonio Miele","raw_affiliation_strings":["Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano, Milan, Italy"],"raw_orcid":"https://orcid.org/0000-0003-3197-0723","affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano, Milan, Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5056188563","display_name":"John Lillis","orcid":null},"institutions":[{"id":"https://openalex.org/I39422238","display_name":"University of Illinois Chicago","ror":"https://ror.org/02mpq6x41","country_code":"US","type":"education","lineage":["https://openalex.org/I39422238"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"John Lillis","raw_affiliation_strings":["The University of Illinois at Chicago, Chicago, IL, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"The University of Illinois at Chicago, Chicago, IL, USA","institution_ids":["https://openalex.org/I39422238"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5010543929","display_name":"Marco D. Santambrogio","orcid":"https://orcid.org/0000-0002-9883-9693"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Marco Domenico Santambrogio","raw_affiliation_strings":["Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano, Milan, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano, Milan, Italy","institution_ids":["https://openalex.org/I93860229"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":2.4948,"has_fulltext":false,"cited_by_count":36,"citation_normalized_percentile":{"value":0.89868403,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":98},"biblio":{"volume":"25","issue":"1","first_page":"151","last_page":"164"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/floorplan","display_name":"Floorplan","score":0.8964760303497314},{"id":"https://openalex.org/keywords/automation","display_name":"Automation","score":0.6973842978477478},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6133559942245483},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5319583415985107},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4476734697818756},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.38736575841903687},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.32353475689888},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2575215697288513}],"concepts":[{"id":"https://openalex.org/C130145326","wikidata":"https://www.wikidata.org/wiki/Q1553985","display_name":"Floorplan","level":2,"score":0.8964760303497314},{"id":"https://openalex.org/C115901376","wikidata":"https://www.wikidata.org/wiki/Q184199","display_name":"Automation","level":2,"score":0.6973842978477478},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6133559942245483},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5319583415985107},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4476734697818756},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.38736575841903687},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.32353475689888},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2575215697288513},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/tvlsi.2016.2562361","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2016.2562361","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},{"id":"pmh:oai:re.public.polimi.it:11311/1006255","is_oa":true,"landing_page_url":"http://hdl.handle.net/11311/1006255","pdf_url":null,"source":{"id":"https://openalex.org/S4306400312","display_name":"Virtual Community of Pathological Anatomy (University of Castilla La Mancha)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I79189158","host_organization_name":"University of Castilla-La Mancha","host_organization_lineage":["https://openalex.org/I79189158"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/article"},{"id":"pmh:oai:zenodo.org:3453655","is_oa":true,"landing_page_url":"https://zenodo.org/record/3453655","pdf_url":null,"source":{"id":"https://openalex.org/S4306400562","display_name":"Zenodo (CERN European Organization for Nuclear Research)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I67311998","host_organization_name":"European Organization for Nuclear Research","host_organization_lineage":["https://openalex.org/I67311998"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/article"}],"best_oa_location":{"id":"pmh:oai:re.public.polimi.it:11311/1006255","is_oa":true,"landing_page_url":"http://hdl.handle.net/11311/1006255","pdf_url":null,"source":{"id":"https://openalex.org/S4306400312","display_name":"Virtual Community of Pathological Anatomy (University of Castilla La Mancha)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I79189158","host_organization_name":"University of Castilla-La Mancha","host_organization_lineage":["https://openalex.org/I79189158"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/article"},"sustainable_development_goals":[{"display_name":"Sustainable cities and communities","id":"https://metadata.un.org/sdg/11","score":0.4300000071525574}],"awards":[{"id":"https://openalex.org/G2879175600","display_name":"Exploiting eXascale Technology with Reconfigurable Architectures","funder_award_id":"671653","funder_id":"https://openalex.org/F4320320300","funder_display_name":"European Commission"}],"funders":[{"id":"https://openalex.org/F4320320300","display_name":"European Commission","ror":"https://ror.org/00k4n6c32"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":25,"referenced_works":["https://openalex.org/W3129724","https://openalex.org/W92551552","https://openalex.org/W114936159","https://openalex.org/W165160209","https://openalex.org/W1483017465","https://openalex.org/W1594617929","https://openalex.org/W1966195532","https://openalex.org/W2005730042","https://openalex.org/W2007945515","https://openalex.org/W2030767815","https://openalex.org/W2034729118","https://openalex.org/W2070215512","https://openalex.org/W2071315556","https://openalex.org/W2102823893","https://openalex.org/W2111034061","https://openalex.org/W2114772983","https://openalex.org/W2120785033","https://openalex.org/W2131455863","https://openalex.org/W2133059825","https://openalex.org/W2154940055","https://openalex.org/W3023540311","https://openalex.org/W4243796313","https://openalex.org/W6604701370","https://openalex.org/W6680096826","https://openalex.org/W6682747291"],"related_works":["https://openalex.org/W2055008360","https://openalex.org/W2135118255","https://openalex.org/W215057456","https://openalex.org/W1500063550","https://openalex.org/W2180598069","https://openalex.org/W2261987718","https://openalex.org/W2983230882","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506"],"abstract_inverted_index":{"When":[0],"dealing":[1],"with":[2,77,100,148],"partially":[3],"reconfigurable":[4],"designs":[5],"on":[6,58,87,123],"field-programmable":[7],"gate":[8],"array,":[9],"floorplanning":[10,46,85],"represents":[11],"a":[12,44,72,78,101],"critical":[13],"step":[14],"that":[15],"highly":[16],"impacts":[17],"system's":[18],"performance":[19],"and":[20,105,119,140,159],"reconfiguration":[21],"overhead.":[22],"However,":[23],"current":[24],"vendor":[25],"design":[26],"tools":[27],"still":[28],"require":[29],"the":[30,37,51,63,84,88,111,116,124,132,135,141,144,151],"floorplan":[31],"to":[32,82,150],"be":[33],"manually":[34],"defined":[35,89,145],"by":[36],"designer.":[38],"Within":[39],"this":[40],"paper,":[41],"we":[42,70],"provide":[43],"novel":[45],"automation":[47],"framework,":[48],"integrated":[49],"in":[50,154],"Xilinx":[52],"tool":[53],"chain,":[54],"which":[55],"is":[56],"based":[57,122],"an":[59],"explicit":[60],"enumeration":[61],"of":[62,66,134,143,156],"possible":[64],"placements":[65],"each":[67],"region.":[68],"Moreover,":[69],"propose":[71],"genetic":[73],"algorithm":[74],"(GA),":[75],"enhanced":[76],"local":[79],"search":[80],"strategy,":[81],"automate":[83],"activity":[86],"direct":[90,126,137],"problem":[91,127,138],"representation.":[92,128],"The":[93],"proposed":[94,136],"approach":[95],"has":[96],"been":[97],"experimentally":[98],"evaluated":[99],"synthetic":[102],"benchmark":[103],"suite":[104],"real":[106],"case":[107],"studies.":[108],"We":[109],"compared":[110],"designed":[112],"solution":[113],"against":[114],"both":[115],"state-of-the-art":[117],"algorithms":[118],"alternative":[120],"engines":[121],"same":[125],"Experimental":[129],"results":[130],"demonstrated":[131],"effectiveness":[133],"representation":[139],"superiority":[142],"GA":[146],"engine":[147],"respect":[149],"other":[152],"approaches":[153],"terms":[155],"exploration":[157],"time":[158],"identified":[160],"solution.":[161]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":6},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":5},{"year":2020,"cited_by_count":5},{"year":2019,"cited_by_count":4},{"year":2018,"cited_by_count":5},{"year":2017,"cited_by_count":5}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}