{"id":"https://openalex.org/W2347197634","doi":"https://doi.org/10.1109/tvlsi.2016.2556943","title":"Optimizing the Implementation of SEC\u2013DAEC Codes in FPGAs","display_name":"Optimizing the Implementation of SEC\u2013DAEC Codes in FPGAs","publication_year":2016,"publication_date":"2016-05-02","ids":{"openalex":"https://openalex.org/W2347197634","doi":"https://doi.org/10.1109/tvlsi.2016.2556943","mag":"2347197634"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2016.2556943","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2016.2556943","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5078857723","display_name":"Alfonso S\u00e1nchez\u2010Maci\u00e1n","orcid":"https://orcid.org/0000-0002-2220-0594"},"institutions":[{"id":"https://openalex.org/I3020445194","display_name":"Universidad Nebrija","ror":"https://ror.org/03tzyrt94","country_code":"ES","type":"education","lineage":["https://openalex.org/I3020445194"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Alfonso Sanchez-Macian","raw_affiliation_strings":["Universidad Antonio de Nebrija, Madrid, Spain"],"raw_orcid":"https://orcid.org/0000-0002-2220-0594","affiliations":[{"raw_affiliation_string":"Universidad Antonio de Nebrija, Madrid, Spain","institution_ids":["https://openalex.org/I3020445194"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5080322790","display_name":"Pedro Reviriego","orcid":"https://orcid.org/0000-0003-2540-5234"},"institutions":[{"id":"https://openalex.org/I3020445194","display_name":"Universidad Nebrija","ror":"https://ror.org/03tzyrt94","country_code":"ES","type":"education","lineage":["https://openalex.org/I3020445194"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Pedro Reviriego","raw_affiliation_strings":["Universidad Antonio de Nebrija, Madrid, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Universidad Antonio de Nebrija, Madrid, Spain","institution_ids":["https://openalex.org/I3020445194"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5044495372","display_name":"Juan Antonio Maestro","orcid":"https://orcid.org/0000-0001-7133-9026"},"institutions":[{"id":"https://openalex.org/I3020445194","display_name":"Universidad Nebrija","ror":"https://ror.org/03tzyrt94","country_code":"ES","type":"education","lineage":["https://openalex.org/I3020445194"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Juan Antonio Maestro","raw_affiliation_strings":["Universidad Antonio de Nebrija, Madrid, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Universidad Antonio de Nebrija, Madrid, Spain","institution_ids":["https://openalex.org/I3020445194"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I3020445194"],"apc_list":null,"apc_paid":null,"fwci":0.3564,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.63306344,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"24","issue":"12","first_page":"3538","last_page":"3542"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9965000152587891,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7650305032730103},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7472398281097412},{"id":"https://openalex.org/keywords/encoder","display_name":"Encoder","score":0.6803263425827026},{"id":"https://openalex.org/keywords/error-detection-and-correction","display_name":"Error detection and correction","score":0.6575027704238892},{"id":"https://openalex.org/keywords/decoding-methods","display_name":"Decoding methods","score":0.4462845027446747},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4178077280521393},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.350899338722229},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3405616581439972},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3310994505882263}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7650305032730103},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7472398281097412},{"id":"https://openalex.org/C118505674","wikidata":"https://www.wikidata.org/wiki/Q42586063","display_name":"Encoder","level":2,"score":0.6803263425827026},{"id":"https://openalex.org/C103088060","wikidata":"https://www.wikidata.org/wiki/Q1062839","display_name":"Error detection and correction","level":2,"score":0.6575027704238892},{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.4462845027446747},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4178077280521393},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.350899338722229},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3405616581439972},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3310994505882263},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2016.2556943","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2016.2556943","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.46000000834465027,"id":"https://metadata.un.org/sdg/8","display_name":"Decent work and economic growth"}],"awards":[{"id":"https://openalex.org/G7611336909","display_name":null,"funder_award_id":"ESP2014-54505-C2-1-R","funder_id":"https://openalex.org/F4320321837","funder_display_name":"Ministerio de Econom\u00eda y Competitividad"}],"funders":[{"id":"https://openalex.org/F4320321837","display_name":"Ministerio de Econom\u00eda y Competitividad","ror":"https://ror.org/034900433"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W2025474944","https://openalex.org/W2035561773","https://openalex.org/W2059625562","https://openalex.org/W2095462161","https://openalex.org/W2100249453","https://openalex.org/W2118637853","https://openalex.org/W2126814059","https://openalex.org/W2134910804","https://openalex.org/W2137972166","https://openalex.org/W2151529344","https://openalex.org/W2159352256","https://openalex.org/W2172099323","https://openalex.org/W2912142228","https://openalex.org/W3145442597"],"related_works":["https://openalex.org/W2392571380","https://openalex.org/W2392153588","https://openalex.org/W1919071401","https://openalex.org/W2352395137","https://openalex.org/W4290803201","https://openalex.org/W3094426418","https://openalex.org/W2384814952","https://openalex.org/W2373066471","https://openalex.org/W1508811950","https://openalex.org/W2349436890"],"abstract_inverted_index":{"Single":[0],"error":[1,5,13],"correction":[2,6,14],"and":[3,21,42],"double-adjacent":[4,22],"(SEC-DAEC)":[7],"codes":[8,15,70],"are":[9,25],"a":[10,45],"type":[11],"of":[12,18,68],"(ECCs)":[16],"capable":[17],"correcting":[19],"single":[20],"errors.":[23],"They":[24],"useful":[26],"in":[27,73],"applications":[28],"where":[29],"multiple":[30],"adjacent":[31],"errors":[32],"may":[33],"occur,":[34],"such":[35],"as":[36],"space":[37],"or":[38],"avionics.":[39],"ECC":[40],"encoders":[41],"decoders":[43],"have":[44],"regular":[46],"structure":[47],"that":[48],"makes":[49],"it":[50],"easier":[51],"to":[52,64],"accommodate":[53],"them":[54],"into":[55],"field-programmable":[56],"gate":[57],"arrays":[58],"(FPGAs).":[59],"This":[60],"brief":[61],"proposes":[62],"methods":[63],"optimize":[65],"the":[66,77,83],"decoder":[67],"SEC-DAEC":[69],"when":[71,80],"implemented":[72],"an":[74],"FPGA,":[75],"reducing":[76],"resource":[78],"utilization":[79],"compared":[81],"with":[82],"conventional":[84],"implementations.":[85]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}