{"id":"https://openalex.org/W2344348048","doi":"https://doi.org/10.1109/tvlsi.2015.2504871","title":"Streaming Elements for FPGA Signal and Image Processing Accelerators","display_name":"Streaming Elements for FPGA Signal and Image Processing Accelerators","publication_year":2016,"publication_date":"2016-01-06","ids":{"openalex":"https://openalex.org/W2344348048","doi":"https://doi.org/10.1109/tvlsi.2015.2504871","mag":"2344348048"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2015.2504871","is_oa":true,"landing_page_url":"https://doi.org/10.1109/tvlsi.2015.2504871","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"hybrid","oa_url":"https://doi.org/10.1109/tvlsi.2015.2504871","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5108049097","display_name":"Peng Wang","orcid":"https://orcid.org/0000-0002-5223-7515"},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Peng Wang","raw_affiliation_strings":["ARM, Cambridge, U.K"],"affiliations":[{"raw_affiliation_string":"ARM, Cambridge, U.K","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5036512274","display_name":"John McAllister","orcid":"https://orcid.org/0000-0002-4017-115X"},"institutions":[{"id":"https://openalex.org/I126231945","display_name":"Queen's University Belfast","ror":"https://ror.org/00hswnk62","country_code":"GB","type":"education","lineage":["https://openalex.org/I126231945"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"John McAllister","raw_affiliation_strings":["Institute of Electronics, Communications and Information Technology, Queen\u2019s University Belfast, Belfast, U.K","Institute of Electronics, Communications and Information Technology, Queen's University Belfast, Belfast, U.K"],"affiliations":[{"raw_affiliation_string":"Institute of Electronics, Communications and Information Technology, Queen\u2019s University Belfast, Belfast, U.K","institution_ids":["https://openalex.org/I126231945"]},{"raw_affiliation_string":"Institute of Electronics, Communications and Information Technology, Queen's University Belfast, Belfast, U.K","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5108049097"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":2.5748,"has_fulltext":true,"cited_by_count":22,"citation_normalized_percentile":{"value":0.88697969,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":"24","issue":"6","first_page":"2262","last_page":"2274"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.699916422367096},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.635069727897644},{"id":"https://openalex.org/keywords/signal-processing","display_name":"Signal processing","score":0.6116740107536316},{"id":"https://openalex.org/keywords/image-processing","display_name":"Image processing","score":0.5638166069984436},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.44512367248535156},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.44426220655441284},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.39517727494239807},{"id":"https://openalex.org/keywords/image","display_name":"Image (mathematics)","score":0.362882137298584},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3416159749031067},{"id":"https://openalex.org/keywords/computer-vision","display_name":"Computer vision","score":0.2508541941642761}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.699916422367096},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.635069727897644},{"id":"https://openalex.org/C104267543","wikidata":"https://www.wikidata.org/wiki/Q208163","display_name":"Signal processing","level":3,"score":0.6116740107536316},{"id":"https://openalex.org/C9417928","wikidata":"https://www.wikidata.org/wiki/Q1070689","display_name":"Image processing","level":3,"score":0.5638166069984436},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.44512367248535156},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.44426220655441284},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.39517727494239807},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.362882137298584},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3416159749031067},{"id":"https://openalex.org/C31972630","wikidata":"https://www.wikidata.org/wiki/Q844240","display_name":"Computer vision","level":1,"score":0.2508541941642761}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/tvlsi.2015.2504871","is_oa":true,"landing_page_url":"https://doi.org/10.1109/tvlsi.2015.2504871","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},{"id":"pmh:oai:pure.qub.ac.uk/portal:openaire/0003b22f-379c-4e7e-b5be-e2ae151377ce","is_oa":true,"landing_page_url":"https://pure.qub.ac.uk/en/publications/0003b22f-379c-4e7e-b5be-e2ae151377ce","pdf_url":"https://pureadmin.qub.ac.uk/ws/files/120577476/Streaming_elements.pdf","source":{"id":"https://openalex.org/S4306402319","display_name":"Research Portal (Queen's University Belfast)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I126231945","host_organization_name":"Queen's University Belfast","host_organization_lineage":["https://openalex.org/I126231945"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Wang, P & McAllister, J 2016, 'Streaming Elements for FPGA Signal and Image Processing Accelerators', IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 6, pp. 2262-2274. https://doi.org/10.1109/TVLSI.2015.2504871","raw_type":"info:eu-repo/semantics/publishedVersion"}],"best_oa_location":{"id":"doi:10.1109/tvlsi.2015.2504871","is_oa":true,"landing_page_url":"https://doi.org/10.1109/tvlsi.2015.2504871","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"sustainable_development_goals":[{"score":0.5199999809265137,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[{"id":"https://openalex.org/G3877790631","display_name":null,"funder_award_id":"EP/H051155/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"},{"id":"https://openalex.org/G768128125","display_name":"Softcore Streaming Processors for FPGA","funder_award_id":"EP/H051155/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"}],"funders":[{"id":"https://openalex.org/F4320334627","display_name":"Engineering and Physical Sciences Research Council","ror":"https://ror.org/0439y7842"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":28,"referenced_works":["https://openalex.org/W107147422","https://openalex.org/W1493456587","https://openalex.org/W1603238397","https://openalex.org/W1970047515","https://openalex.org/W1970340536","https://openalex.org/W1998568329","https://openalex.org/W2000505655","https://openalex.org/W2006381476","https://openalex.org/W2023497162","https://openalex.org/W2024381286","https://openalex.org/W2026534511","https://openalex.org/W2063488795","https://openalex.org/W2081286217","https://openalex.org/W2117099910","https://openalex.org/W2141597697","https://openalex.org/W2146449469","https://openalex.org/W2154881179","https://openalex.org/W2155729354","https://openalex.org/W2160411501","https://openalex.org/W2166029537","https://openalex.org/W2167897136","https://openalex.org/W2264337508","https://openalex.org/W4234246036","https://openalex.org/W4242435189","https://openalex.org/W6604403076","https://openalex.org/W6656165752","https://openalex.org/W6666682030","https://openalex.org/W6693180885"],"related_works":["https://openalex.org/W2352017551","https://openalex.org/W2384742169","https://openalex.org/W2010643833","https://openalex.org/W2349666940","https://openalex.org/W2377087316","https://openalex.org/W4308216800","https://openalex.org/W2384717299","https://openalex.org/W2362272581","https://openalex.org/W2348404350","https://openalex.org/W2002209826"],"abstract_inverted_index":{"Field-programmable":[0],"gate":[1],"array":[2],"(FPGA)":[3],"devices":[4],"boast":[5],"abundant":[6],"resources":[7],"with":[8,104,159,164],"which":[9,90,125],"custom":[10,59,95,166],"accelerator":[11,86],"components":[12],"for":[13,69,136],"signal,":[14],"image,":[15],"and":[16,55,108,123,144,158,161,169],"data":[17],"processing":[18,67],"may":[19],"be":[20,116],"realized;":[21],"however,":[22],"realizing":[23],"high-performance,":[24,78],"low-cost":[25],"accelerators":[26,92,135,168],"currently":[27],"demands":[28],"manual":[29],"register":[30],"transfer":[31],"level":[32],"design.":[33],"Software-programmable":[34],"soft":[35,66,178],"processors":[36],"have":[37],"been":[38],"proposed":[39,153],"as":[40,83,93],"a":[41,64,84,100],"way":[42],"to":[43,52,58,73,120,133,171],"reduce":[44],"this":[45,75],"design":[46],"burden,":[47],"but":[48],"they":[49],"are":[50,126],"unable":[51],"support":[53],"performance":[54,122,157,160],"cost":[56,162],"comparable":[57,163],"circuits.":[60],"This":[61],"paper":[62],"proposes":[63],"new":[65],"approach":[68,103],"FPGA":[70],"that":[71],"promises":[72],"overcome":[74],"barrier.":[76],"A":[77],"fine-grained":[79],"streaming":[80,85,101],"processor,":[81],"known":[82],"element,":[87],"is":[88,149],"proposed,":[89],"realizes":[91],"large-scale":[94],"multicore":[96],"networks.":[97],"By":[98],"adopting":[99],"execution":[102],"advanced":[105],"program":[106,113],"control":[107],"memory":[109],"addressing":[110],"capabilities,":[111],"typical":[112],"inefficiencies":[114],"can":[115],"almost":[117],"completely":[118],"eliminated":[119],"enable":[121],"cost,":[124],"unprecedented":[127],"among":[128],"software-programmable":[129],"solutions.":[130],"When":[131],"used":[132],"realize":[134],"fast":[137],"Fourier":[138],"transform,":[139],"motion":[140],"estimation,":[141],"matrix":[142],"multiplication,":[143],"sobel":[145],"edge":[146],"detection,":[147],"it":[148],"shown":[150],"how":[151],"the":[152],"architecture":[154],"enables":[155],"real-time":[156],"hand-crafted":[165],"circuit":[167],"up":[170],"two":[172],"orders":[173],"of":[174],"magnitude":[175],"beyond":[176],"existing":[177],"processors.":[179]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":1},{"year":2022,"cited_by_count":6},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":4},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":5}],"updated_date":"2026-03-17T17:19:04.345684","created_date":"2025-10-10T00:00:00"}
