{"id":"https://openalex.org/W2338617962","doi":"https://doi.org/10.1109/tvlsi.2015.2474129","title":"Memory-Aware Loop Mapping on Coarse-Grained Reconfigurable Architectures","display_name":"Memory-Aware Loop Mapping on Coarse-Grained Reconfigurable Architectures","publication_year":2015,"publication_date":"2015-09-22","ids":{"openalex":"https://openalex.org/W2338617962","doi":"https://doi.org/10.1109/tvlsi.2015.2474129","mag":"2338617962"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2015.2474129","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2015.2474129","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5054524841","display_name":"Shouyi Yin","orcid":"https://orcid.org/0000-0003-2309-572X"},"institutions":[{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]},{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Shouyi Yin","raw_affiliation_strings":["Institute of Microelectronics, Tsinghua University, Beijing, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Microelectronics, Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I4210119392","https://openalex.org/I99065089"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110466012","display_name":"Xianqing Yao","orcid":null},"institutions":[{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]},{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xianqing Yao","raw_affiliation_strings":["Institute of Microelectronics, Tsinghua University, Beijing, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Microelectronics, Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I4210119392","https://openalex.org/I99065089"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102986560","display_name":"Dajiang Liu","orcid":"https://orcid.org/0000-0002-1591-0635"},"institutions":[{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]},{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Dajiang Liu","raw_affiliation_strings":["Institute of Microelectronics, Tsinghua University, Beijing, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Microelectronics, Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I4210119392","https://openalex.org/I99065089"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100358856","display_name":"Leibo Liu","orcid":"https://orcid.org/0000-0001-7548-4116"},"institutions":[{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]},{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Leibo Liu","raw_affiliation_strings":["Institute of Microelectronics, Tsinghua University, Beijing, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Microelectronics, Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I4210119392","https://openalex.org/I99065089"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5036023084","display_name":"Shaojun Wei","orcid":"https://orcid.org/0000-0001-5117-7920"},"institutions":[{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]},{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Shaojun Wei","raw_affiliation_strings":["Institute of Microelectronics, Tsinghua University, Beijing, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Microelectronics, Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I4210119392","https://openalex.org/I99065089"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":5.3317,"has_fulltext":false,"cited_by_count":41,"citation_normalized_percentile":{"value":0.9552005,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":91,"max":99},"biblio":{"volume":"24","issue":"5","first_page":"1895","last_page":"1908"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8348129987716675},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.7227248549461365},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.5908066034317017},{"id":"https://openalex.org/keywords/memory-bandwidth","display_name":"Memory bandwidth","score":0.5430317521095276},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5218355059623718},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.487337201833725},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.47375091910362244},{"id":"https://openalex.org/keywords/modulo","display_name":"Modulo","score":0.4723342955112457},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3943588137626648},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.27245065569877625},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.13416242599487305}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8348129987716675},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.7227248549461365},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.5908066034317017},{"id":"https://openalex.org/C188045654","wikidata":"https://www.wikidata.org/wiki/Q17148339","display_name":"Memory bandwidth","level":2,"score":0.5430317521095276},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5218355059623718},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.487337201833725},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.47375091910362244},{"id":"https://openalex.org/C54732982","wikidata":"https://www.wikidata.org/wiki/Q1415345","display_name":"Modulo","level":2,"score":0.4723342955112457},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3943588137626648},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.27245065569877625},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.13416242599487305},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2015.2474129","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2015.2474129","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G3907330648","display_name":null,"funder_award_id":"61274131","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"}],"funders":[{"id":"https://openalex.org/F4320321001","display_name":"National Natural Science Foundation of China","ror":"https://ror.org/01h0zpd94"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":36,"referenced_works":["https://openalex.org/W201652765","https://openalex.org/W1565617730","https://openalex.org/W1964191474","https://openalex.org/W1966326666","https://openalex.org/W1981307085","https://openalex.org/W1996906769","https://openalex.org/W1997358129","https://openalex.org/W2008020492","https://openalex.org/W2021552071","https://openalex.org/W2023027709","https://openalex.org/W2025787141","https://openalex.org/W2034919602","https://openalex.org/W2035473608","https://openalex.org/W2059628517","https://openalex.org/W2067683688","https://openalex.org/W2082403159","https://openalex.org/W2087476542","https://openalex.org/W2087847273","https://openalex.org/W2098908185","https://openalex.org/W2100027188","https://openalex.org/W2117105306","https://openalex.org/W2117385926","https://openalex.org/W2122171990","https://openalex.org/W2123565700","https://openalex.org/W2141280299","https://openalex.org/W2149102736","https://openalex.org/W2153883804","https://openalex.org/W2155884182","https://openalex.org/W2159108969","https://openalex.org/W2168921806","https://openalex.org/W2172212694","https://openalex.org/W3150601291","https://openalex.org/W4231951809","https://openalex.org/W4232014589","https://openalex.org/W4250523893","https://openalex.org/W4254944975"],"related_works":["https://openalex.org/W2117548279","https://openalex.org/W2807449856","https://openalex.org/W238211858","https://openalex.org/W2070252991","https://openalex.org/W2154356865","https://openalex.org/W2077105843","https://openalex.org/W2770465587","https://openalex.org/W2086716781","https://openalex.org/W2022510519","https://openalex.org/W2769711393"],"abstract_inverted_index":{"The":[0,21,142],"coarse-grained":[1],"reconfigurable":[2],"architectures":[3,10],"(CGRAs)":[4],"are":[5,29,67],"a":[6,89,113,128],"promising":[7],"class":[8],"of":[9,14,24,42,74,91,98,147,163],"with":[11,83,176,187],"the":[12,33,39,46,51,64,71,96,99,117,148,161,164,177],"advantages":[13],"high":[15,18],"performance":[16,162],"and":[17,45,56,79,94,131,151,173,183],"power":[19],"efficiency.":[20],"compute-intensive":[22],"parts":[23],"an":[25,134,188],"application":[26],"(e.g.,":[27,77],"loops)":[28],"often":[30],"mapped":[31],"onto":[32],"CGRA":[34,118,167],"for":[35,116,137],"acceleration.":[36],"Due":[37],"to":[38,62,140,169],"extra":[40],"overhead":[41],"memory":[43,126],"access":[44],"limited":[47],"communication":[48],"bandwidth":[49],"between":[50],"processing":[52],"element":[53],"(PE)":[54],"array":[55],"local":[57,124],"memory,":[58],"previous":[59],"works":[60],"trying":[61],"solve":[63,103],"routing":[65,82,129],"problem":[66,120],"mainly":[68],"confined":[69],"in":[70,191],"internal":[72],"resources":[73,93],"PE":[75],"arrays":[76],"PEs":[78,84],"registers).":[80],"Inevitably,":[81],"or":[85],"registers":[86],"will":[87],"consume":[88],"lot":[90],"computational":[92],"cause":[95],"increase":[97,190],"initiation":[100],"interval.":[101],"To":[102],"this":[104,106],"problem,":[105],"paper":[107],"makes":[108],"two":[109],"contributions:":[110],"1)":[111],"establishing":[112],"precise":[114],"formulation":[115],"mapping":[119,138],"while":[121],"using":[122],"shared":[123],"data":[125],"as":[127],"resource":[130],"2)":[132],"extracting":[133],"effective":[135],"approach":[136,156],"loops":[139,146],"CGRAs.":[141],"experimental":[143],"results":[144],"on":[145,166],"SPEC2006,":[149],"Livermore,":[150],"MiBench":[152],"show":[153],"that":[154],"our":[155],"(called":[157],"MEMMap)":[158],"can":[159],"improve":[160],"kernels":[165],"up":[168],"1.62\u00d7,":[170],"1.58\u00d7,":[171],"1.28\u00d7,":[172],"1.23\u00d7":[174],"compared":[175],"edge-centric":[178],"modulo":[179],"scheduling,":[180],"EPIMap,":[181],"REGIMap,":[182],"force-directed":[184],"map,":[185],"respectively,":[186],"acceptable":[189],"compilation":[192],"time.":[193]},"counts_by_year":[{"year":2026,"cited_by_count":2},{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":7},{"year":2021,"cited_by_count":4},{"year":2020,"cited_by_count":6},{"year":2019,"cited_by_count":6},{"year":2018,"cited_by_count":6},{"year":2017,"cited_by_count":3},{"year":2016,"cited_by_count":2}],"updated_date":"2026-07-22T07:51:19.307946","created_date":"2025-10-10T00:00:00"}