{"id":"https://openalex.org/W2311138135","doi":"https://doi.org/10.1109/tvlsi.2015.2450500","title":"Full-Swing Local Bitline SRAM Architecture Based on the 22-nm FinFET Technology for Low-Voltage Operation","display_name":"Full-Swing Local Bitline SRAM Architecture Based on the 22-nm FinFET Technology for Low-Voltage Operation","publication_year":2015,"publication_date":"2015-08-13","ids":{"openalex":"https://openalex.org/W2311138135","doi":"https://doi.org/10.1109/tvlsi.2015.2450500","mag":"2311138135"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2015.2450500","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2015.2450500","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5031307642","display_name":"Kyoman Kang","orcid":null},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Kyoman Kang","raw_affiliation_strings":["School of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea","institution_ids":["https://openalex.org/I193775966"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108522065","display_name":"Hanwool Jeong","orcid":null},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Hanwool Jeong","raw_affiliation_strings":["School of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea","institution_ids":["https://openalex.org/I193775966"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109509787","display_name":"Younghwi Yang","orcid":null},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Younghwi Yang","raw_affiliation_strings":["School of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea","institution_ids":["https://openalex.org/I193775966"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101793550","display_name":"Juhyun Park","orcid":"https://orcid.org/0000-0003-4631-442X"},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Juhyun Park","raw_affiliation_strings":["School of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea","institution_ids":["https://openalex.org/I193775966"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5066554241","display_name":"Kiryong Kim","orcid":"https://orcid.org/0000-0002-2256-3782"},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Kiryong Kim","raw_affiliation_strings":["School of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea","institution_ids":["https://openalex.org/I193775966"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5037010076","display_name":"Seong\u2010Ook Jung","orcid":"https://orcid.org/0000-0003-0757-2581"},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Seong-Ook Jung","raw_affiliation_strings":["School of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea","institution_ids":["https://openalex.org/I193775966"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.6067,"has_fulltext":false,"cited_by_count":21,"citation_normalized_percentile":{"value":0.85888295,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":"24","issue":"4","first_page":"1342","last_page":"1350"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.8570533990859985},{"id":"https://openalex.org/keywords/swing","display_name":"Swing","score":0.7668635845184326},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.5576902627944946},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.5185373425483704},{"id":"https://openalex.org/keywords/random-access-memory","display_name":"Random access memory","score":0.5147645473480225},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.48746585845947266},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.47752490639686584},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.4623635411262512},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.4469432830810547},{"id":"https://openalex.org/keywords/threshold-voltage","display_name":"Threshold voltage","score":0.4404899477958679},{"id":"https://openalex.org/keywords/optoelectronics","display_name":"Optoelectronics","score":0.4219406843185425},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.3442051112651825},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.30501097440719604},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.2562750279903412},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.17360389232635498}],"concepts":[{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.8570533990859985},{"id":"https://openalex.org/C65655974","wikidata":"https://www.wikidata.org/wiki/Q14867674","display_name":"Swing","level":2,"score":0.7668635845184326},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.5576902627944946},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.5185373425483704},{"id":"https://openalex.org/C2994168587","wikidata":"https://www.wikidata.org/wiki/Q5295","display_name":"Random access memory","level":2,"score":0.5147645473480225},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.48746585845947266},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.47752490639686584},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.4623635411262512},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.4469432830810547},{"id":"https://openalex.org/C195370968","wikidata":"https://www.wikidata.org/wiki/Q1754002","display_name":"Threshold voltage","level":4,"score":0.4404899477958679},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.4219406843185425},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.3442051112651825},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.30501097440719604},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.2562750279903412},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.17360389232635498},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2015.2450500","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2015.2450500","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.4399999976158142}],"awards":[{"id":"https://openalex.org/G8575699015","display_name":null,"funder_award_id":"10039174","funder_id":"https://openalex.org/F4320321640","funder_display_name":"Ministry of Knowledge Economy"}],"funders":[{"id":"https://openalex.org/F4320321640","display_name":"Ministry of Knowledge Economy","ror":"https://ror.org/008nkqk13"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1984048874","https://openalex.org/W1989227777","https://openalex.org/W2075848529","https://openalex.org/W2078953735","https://openalex.org/W2093108103","https://openalex.org/W2095913060","https://openalex.org/W2099087448","https://openalex.org/W2105175332","https://openalex.org/W2106339466","https://openalex.org/W2120203087","https://openalex.org/W2144289559","https://openalex.org/W2162517322","https://openalex.org/W2172173999","https://openalex.org/W2546044294","https://openalex.org/W6670143336","https://openalex.org/W6677529475"],"related_works":["https://openalex.org/W2089002058","https://openalex.org/W1909296377","https://openalex.org/W3185029353","https://openalex.org/W3116379964","https://openalex.org/W2766443086","https://openalex.org/W2915176329","https://openalex.org/W2793465010","https://openalex.org/W2967161359","https://openalex.org/W2032691814","https://openalex.org/W2621979731"],"abstract_inverted_index":{"The":[0,213],"previously":[1],"proposed":[2,147,193,214],"average-8T":[3,25,58,244],"static":[4],"random":[5],"access":[6],"memory":[7],"(SRAM)":[8],"has":[9],"a":[10,17,28,47,67,96,121,134,139,174,225,232],"competitive":[11],"area":[12,210],"and":[13,103,164,209,231],"does":[14],"not":[15],"require":[16],"write-back":[18],"scheme.":[19],"In":[20,145],"the":[21,37,40,54,72,79,89,93,104,107,114,128,146,153,159,165,168,182,185,192,205,243,248],"case":[22,55],"of":[23,39,56,92,106,152,161,167,191,204,228,242],"an":[24,57,62],"SRAM":[26,59,136,148,194,215,245],"architecture,":[27,149,195],"full-swing":[29,97,140],"local":[30,98,141,154],"bitline":[31],"(BL)":[32],"that":[33,216,235,241],"is":[34,77,143,156,171,236],"connected":[35],"to":[36],"gate":[38,105,166],"read":[41,90,108,124,169,233],"buffer":[42,109,170],"can":[43,223],"be":[44,84,101,111],"achieved":[45],"with":[46,138],"boosted":[48,80,186],"wordline":[49],"(WL)":[50],"voltage.":[51,188],"However,":[52],"in":[53,74,120,131,202,220],"based":[60,246],"on":[61,247],"advanced":[63],"technology,":[64,70],"such":[65],"as":[66],"22-nm":[68,249],"FinFET":[69,250],"where":[71],"variation":[73],"threshold":[75],"voltage":[76,82,117,208,227],"large,":[78],"WL":[81,187],"cannot":[83,100,110],"used,":[85],"because":[86],"it":[87],"degrades":[88],"stability":[91],"SRAM.":[94],"Thus,":[95],"BL":[99,142,155],"achieved,":[102],"driven":[112,172],"by":[113,158,173],"full":[115,150,175],"supply":[116],"(VDD),":[118],"resulting":[119],"considerably":[122],"large":[123],"delay.":[125],"To":[126],"overcome":[127],"above":[129],"disadvantage,":[130],"this":[132],"paper,":[133],"differential":[135],"architecture":[137],"proposed.":[144],"swing":[151],"ensured":[157],"use":[160],"cross-coupled":[162],"pMOSs,":[163],"V":[176,230],"<sub":[177],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[178],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">DD</sub>":[179],",":[180],"without":[181],"need":[183],"for":[184],"Various":[189],"configurations":[190],"which":[196],"stores":[197,217],"multiple":[198],"bits,":[199],"are":[200],"analyzed":[201],"terms":[203],"minimum":[206,226],"operating":[207],"per":[211],"bit.":[212],"four":[218],"bits":[219],"one":[221],"block":[222],"achieve":[224],"0.42":[229],"delay":[234],"62.6":[237],"times":[238],"lesser":[239],"than":[240],"technology.":[251]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":2},{"year":2018,"cited_by_count":4},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":2}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
