{"id":"https://openalex.org/W2312163514","doi":"https://doi.org/10.1109/tvlsi.2015.2445855","title":"Concept, Design, and Implementation of Reconfigurable CORDIC","display_name":"Concept, Design, and Implementation of Reconfigurable CORDIC","publication_year":2015,"publication_date":"2015-07-08","ids":{"openalex":"https://openalex.org/W2312163514","doi":"https://doi.org/10.1109/tvlsi.2015.2445855","mag":"2312163514"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2015.2445855","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2015.2445855","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5026026510","display_name":"Supriya Aggarwal","orcid":"https://orcid.org/0000-0002-1976-9579"},"institutions":[{"id":"https://openalex.org/I91277730","display_name":"Maulana Azad National Institute of Technology","ror":"https://ror.org/026vtd268","country_code":"IN","type":"education","lineage":["https://openalex.org/I91277730"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Supriya Aggarwal","raw_affiliation_strings":["Department of Electronics and Communication Engineering, National Institute of Technology, Bhopal, India"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Communication Engineering, National Institute of Technology, Bhopal, India","institution_ids":["https://openalex.org/I91277730"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5025809855","display_name":"Pramod Kumar Meher","orcid":"https://orcid.org/0000-0003-0992-1159"},"institutions":[{"id":"https://openalex.org/I172675005","display_name":"Nanyang Technological University","ror":"https://ror.org/02e7b5302","country_code":"SG","type":"education","lineage":["https://openalex.org/I172675005"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Pramod K. Meher","raw_affiliation_strings":["School of Computer Engineering, Nanyang Technological University, Singapore"],"affiliations":[{"raw_affiliation_string":"School of Computer Engineering, Nanyang Technological University, Singapore","institution_ids":["https://openalex.org/I172675005"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5083830820","display_name":"Kavita Khare","orcid":"https://orcid.org/0000-0002-7704-7646"},"institutions":[{"id":"https://openalex.org/I91277730","display_name":"Maulana Azad National Institute of Technology","ror":"https://ror.org/026vtd268","country_code":"IN","type":"education","lineage":["https://openalex.org/I91277730"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Kavita Khare","raw_affiliation_strings":["Department of Electronics and Communication Engineering, National Institute of Technology, Bhopal, India"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Communication Engineering, National Institute of Technology, Bhopal, India","institution_ids":["https://openalex.org/I91277730"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5026026510"],"corresponding_institution_ids":["https://openalex.org/I91277730"],"apc_list":null,"apc_paid":null,"fwci":3.5052,"has_fulltext":false,"cited_by_count":65,"citation_normalized_percentile":{"value":0.93360353,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":"24","issue":"4","first_page":"1588","last_page":"1592"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.991100013256073,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9824000000953674,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cordic","display_name":"CORDIC","score":0.9840683341026306},{"id":"https://openalex.org/keywords/hyperbolic-function","display_name":"Hyperbolic function","score":0.6814792156219482},{"id":"https://openalex.org/keywords/rotation","display_name":"Rotation (mathematics)","score":0.6145519018173218},{"id":"https://openalex.org/keywords/trigonometric-functions","display_name":"Trigonometric functions","score":0.4833614230155945},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4766950309276581},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.41711682081222534},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.33158332109451294},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.3275441527366638},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.2778547704219818},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.21173226833343506},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.20956900715827942},{"id":"https://openalex.org/keywords/geometry","display_name":"Geometry","score":0.13413861393928528},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.06839749217033386}],"concepts":[{"id":"https://openalex.org/C58870171","wikidata":"https://www.wikidata.org/wiki/Q116076","display_name":"CORDIC","level":3,"score":0.9840683341026306},{"id":"https://openalex.org/C92047909","wikidata":"https://www.wikidata.org/wiki/Q204034","display_name":"Hyperbolic function","level":2,"score":0.6814792156219482},{"id":"https://openalex.org/C74050887","wikidata":"https://www.wikidata.org/wiki/Q848368","display_name":"Rotation (mathematics)","level":2,"score":0.6145519018173218},{"id":"https://openalex.org/C178009071","wikidata":"https://www.wikidata.org/wiki/Q93344","display_name":"Trigonometric functions","level":2,"score":0.4833614230155945},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4766950309276581},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.41711682081222534},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.33158332109451294},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.3275441527366638},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.2778547704219818},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.21173226833343506},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.20956900715827942},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.13413861393928528},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.06839749217033386}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2015.2445855","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2015.2445855","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1853423920","https://openalex.org/W1985956780","https://openalex.org/W1993105390","https://openalex.org/W2028032470","https://openalex.org/W2057789075","https://openalex.org/W2081735895","https://openalex.org/W2100437717","https://openalex.org/W2108300431","https://openalex.org/W2128520477","https://openalex.org/W2142885599","https://openalex.org/W2150633168","https://openalex.org/W2151151478"],"related_works":["https://openalex.org/W4377141943","https://openalex.org/W2053507660","https://openalex.org/W2098264936","https://openalex.org/W2484877567","https://openalex.org/W2041945303","https://openalex.org/W2610656341","https://openalex.org/W1853423920","https://openalex.org/W2130871762","https://openalex.org/W4317829640","https://openalex.org/W2368314690"],"abstract_inverted_index":{"This":[0],"brief":[1],"presents":[2],"the":[3,45,95,108,158],"key":[4],"concept,":[5],"design":[6,160],"strategy,":[7],"and":[8,50,80,83,100,113,118,123,147],"implementation":[9],"of":[10,47,94,110,121,154],"reconfigurable":[11,56,61,75,87,104,162],"coordinate":[12],"rotation":[13,32],"digital":[14,141],"computer":[15],"(CORDIC)":[16],"architectures":[17],"that":[18,64,89],"can":[19,90,106,137],"be":[20,40,138],"configured":[21],"to":[22,42],"operate":[23,91],"either":[24,66,127],"for":[25,28,67,70,78,97,161],"circular":[26,49,68,79,99,122],"or":[27,69,129],"hyperbolic":[29,51,71,81,101,124],"trajectories":[30],"in":[31,92,132,140],"as":[33,35],"well":[34],"vectoring-modes.":[36],"It":[37,136,150],"can,":[38],"therefore,":[39],"used":[41,139],"perform":[43,107],"all":[44],"functions":[46],"both":[48,98],"CORDIC.":[52],"We":[53],"propose":[54],"three":[55],"CORDIC":[57,63,77,88,105,125,131],"designs:":[58],"1)":[59],"a":[60,74,85],"rotation-mode":[62,128],"operates":[65],"trajectory;":[72],"2)":[73],"vectoring-mode":[76,130],"trajectories;":[82],"3)":[84],"generalized":[86],"any":[93],"modes":[96],"trajectories.":[102],"The":[103],"computation":[109],"various":[111],"trigonometric":[112],"exponential":[114],"functions,":[115],"logarithms,":[116],"square-root,":[117],"so":[119,148],"on":[120],"using":[126],"one":[133],"single":[134],"circuit.":[135],"synchronizers,":[142],"graphics":[143],"processors,":[144],"scientific":[145],"calculators,":[146],"on.":[149],"offers":[151],"substantial":[152],"saving":[153],"area":[155],"complexity":[156],"over":[157],"conventional":[159],"applications.":[163]},"counts_by_year":[{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":9},{"year":2023,"cited_by_count":8},{"year":2022,"cited_by_count":11},{"year":2021,"cited_by_count":5},{"year":2020,"cited_by_count":9},{"year":2019,"cited_by_count":10},{"year":2018,"cited_by_count":3},{"year":2017,"cited_by_count":6},{"year":2016,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}