{"id":"https://openalex.org/W2276531971","doi":"https://doi.org/10.1109/tvlsi.2015.2440392","title":"Modeling and Optimization of Memristor and STT-RAM-Based Memory for Low-Power Applications","display_name":"Modeling and Optimization of Memristor and STT-RAM-Based Memory for Low-Power Applications","publication_year":2015,"publication_date":"2015-06-23","ids":{"openalex":"https://openalex.org/W2276531971","doi":"https://doi.org/10.1109/tvlsi.2015.2440392","mag":"2276531971"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2015.2440392","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2015.2440392","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5047341631","display_name":"Yasmin Halawani","orcid":"https://orcid.org/0000-0001-9617-5080"},"institutions":[{"id":"https://openalex.org/I176601375","display_name":"Khalifa University of Science and Technology","ror":"https://ror.org/05hffr360","country_code":"AE","type":"education","lineage":["https://openalex.org/I176601375"]}],"countries":["AE"],"is_corresponding":true,"raw_author_name":"Yasmin Halawani","raw_affiliation_strings":["Department of Electrical and Electronics Engineering, Khalifa University, Abu Dhabi, UAE"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronics Engineering, Khalifa University, Abu Dhabi, UAE","institution_ids":["https://openalex.org/I176601375"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5013814572","display_name":"Baker Mohammad","orcid":"https://orcid.org/0000-0002-6063-473X"},"institutions":[{"id":"https://openalex.org/I176601375","display_name":"Khalifa University of Science and Technology","ror":"https://ror.org/05hffr360","country_code":"AE","type":"education","lineage":["https://openalex.org/I176601375"]}],"countries":["AE"],"is_corresponding":false,"raw_author_name":"Baker Mohammad","raw_affiliation_strings":["Department of Electrical and Electronics Engineering, Khalifa University, Abu Dhabi, UAE"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronics Engineering, Khalifa University, Abu Dhabi, UAE","institution_ids":["https://openalex.org/I176601375"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5067425197","display_name":"Dirar Homouz","orcid":"https://orcid.org/0000-0002-8859-0265"},"institutions":[{"id":"https://openalex.org/I176601375","display_name":"Khalifa University of Science and Technology","ror":"https://ror.org/05hffr360","country_code":"AE","type":"education","lineage":["https://openalex.org/I176601375"]}],"countries":["AE"],"is_corresponding":false,"raw_author_name":"Dirar Homouz","raw_affiliation_strings":["Department of Applied Mathematics and Science, Khalifa University, Abu Dhabi, UAE"],"affiliations":[{"raw_affiliation_string":"Department of Applied Mathematics and Science, Khalifa University, Abu Dhabi, UAE","institution_ids":["https://openalex.org/I176601375"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5020682177","display_name":"Mahmoud Al\u2010Qutayri","orcid":"https://orcid.org/0000-0002-9600-8036"},"institutions":[{"id":"https://openalex.org/I176601375","display_name":"Khalifa University of Science and Technology","ror":"https://ror.org/05hffr360","country_code":"AE","type":"education","lineage":["https://openalex.org/I176601375"]}],"countries":["AE"],"is_corresponding":false,"raw_author_name":"Mahmoud Al-Qutayri","raw_affiliation_strings":["Department of Electrical and Electronics Engineering, Khalifa University, Abu Dhabi, UAE"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronics Engineering, Khalifa University, Abu Dhabi, UAE","institution_ids":["https://openalex.org/I176601375"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5078108496","display_name":"Hani Saleh","orcid":"https://orcid.org/0000-0002-7185-0278"},"institutions":[{"id":"https://openalex.org/I176601375","display_name":"Khalifa University of Science and Technology","ror":"https://ror.org/05hffr360","country_code":"AE","type":"education","lineage":["https://openalex.org/I176601375"]}],"countries":["AE"],"is_corresponding":false,"raw_author_name":"Hani Saleh","raw_affiliation_strings":["Department of Electrical and Electronics Engineering, Khalifa University, Abu Dhabi, UAE"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronics Engineering, Khalifa University, Abu Dhabi, UAE","institution_ids":["https://openalex.org/I176601375"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5047341631"],"corresponding_institution_ids":["https://openalex.org/I176601375"],"apc_list":null,"apc_paid":null,"fwci":3.3539,"has_fulltext":false,"cited_by_count":48,"citation_normalized_percentile":{"value":0.92941017,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":"24","issue":"3","first_page":"1003","last_page":"1014"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.8057569861412048},{"id":"https://openalex.org/keywords/memristor","display_name":"Memristor","score":0.7810360193252563},{"id":"https://openalex.org/keywords/resistive-random-access-memory","display_name":"Resistive random-access memory","score":0.6780511140823364},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6086456179618835},{"id":"https://openalex.org/keywords/universal-memory","display_name":"Universal memory","score":0.5659271478652954},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.5496639609336853},{"id":"https://openalex.org/keywords/memistor","display_name":"Memistor","score":0.5486817359924316},{"id":"https://openalex.org/keywords/non-volatile-random-access-memory","display_name":"Non-volatile random-access memory","score":0.5215334892272949},{"id":"https://openalex.org/keywords/memory-refresh","display_name":"Memory refresh","score":0.5167548060417175},{"id":"https://openalex.org/keywords/non-volatile-memory","display_name":"Non-volatile memory","score":0.5094502568244934},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.481229305267334},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4581966996192932},{"id":"https://openalex.org/keywords/phase-change-memory","display_name":"Phase-change memory","score":0.4565460681915283},{"id":"https://openalex.org/keywords/dynamic-random-access-memory","display_name":"Dynamic random-access memory","score":0.4199822247028351},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.4107045829296112},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.38954561948776245},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.36865895986557007},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2727702260017395},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.25175079703330994},{"id":"https://openalex.org/keywords/computer-memory","display_name":"Computer memory","score":0.2020006775856018}],"concepts":[{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.8057569861412048},{"id":"https://openalex.org/C150072547","wikidata":"https://www.wikidata.org/wiki/Q212923","display_name":"Memristor","level":2,"score":0.7810360193252563},{"id":"https://openalex.org/C182019814","wikidata":"https://www.wikidata.org/wiki/Q1143830","display_name":"Resistive random-access memory","level":3,"score":0.6780511140823364},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6086456179618835},{"id":"https://openalex.org/C195053848","wikidata":"https://www.wikidata.org/wiki/Q7894141","display_name":"Universal memory","level":5,"score":0.5659271478652954},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.5496639609336853},{"id":"https://openalex.org/C1895703","wikidata":"https://www.wikidata.org/wiki/Q6034938","display_name":"Memistor","level":4,"score":0.5486817359924316},{"id":"https://openalex.org/C34172316","wikidata":"https://www.wikidata.org/wiki/Q499024","display_name":"Non-volatile random-access memory","level":5,"score":0.5215334892272949},{"id":"https://openalex.org/C87907426","wikidata":"https://www.wikidata.org/wiki/Q6815755","display_name":"Memory refresh","level":4,"score":0.5167548060417175},{"id":"https://openalex.org/C177950962","wikidata":"https://www.wikidata.org/wiki/Q10997658","display_name":"Non-volatile memory","level":2,"score":0.5094502568244934},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.481229305267334},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4581966996192932},{"id":"https://openalex.org/C64142963","wikidata":"https://www.wikidata.org/wiki/Q1153902","display_name":"Phase-change memory","level":3,"score":0.4565460681915283},{"id":"https://openalex.org/C118702147","wikidata":"https://www.wikidata.org/wiki/Q189396","display_name":"Dynamic random-access memory","level":3,"score":0.4199822247028351},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.4107045829296112},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.38954561948776245},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.36865895986557007},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2727702260017395},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.25175079703330994},{"id":"https://openalex.org/C92855701","wikidata":"https://www.wikidata.org/wiki/Q5830907","display_name":"Computer memory","level":3,"score":0.2020006775856018},{"id":"https://openalex.org/C61696701","wikidata":"https://www.wikidata.org/wiki/Q770766","display_name":"Engineering physics","level":1,"score":0.0},{"id":"https://openalex.org/C133256868","wikidata":"https://www.wikidata.org/wiki/Q7180940","display_name":"Phase change","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2015.2440392","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2015.2440392","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8999999761581421}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":52,"referenced_works":["https://openalex.org/W144150443","https://openalex.org/W178831773","https://openalex.org/W223850716","https://openalex.org/W1965970229","https://openalex.org/W1974831841","https://openalex.org/W1982398126","https://openalex.org/W1985841039","https://openalex.org/W1997611279","https://openalex.org/W2002429125","https://openalex.org/W2003390915","https://openalex.org/W2010423603","https://openalex.org/W2013055927","https://openalex.org/W2013656496","https://openalex.org/W2013902630","https://openalex.org/W2014198201","https://openalex.org/W2018577927","https://openalex.org/W2018774711","https://openalex.org/W2019071604","https://openalex.org/W2038166313","https://openalex.org/W2038493039","https://openalex.org/W2041446224","https://openalex.org/W2047379549","https://openalex.org/W2054904917","https://openalex.org/W2067856946","https://openalex.org/W2094452907","https://openalex.org/W2097268830","https://openalex.org/W2100667760","https://openalex.org/W2109987134","https://openalex.org/W2110697514","https://openalex.org/W2112181056","https://openalex.org/W2113398958","https://openalex.org/W2136811604","https://openalex.org/W2144136224","https://openalex.org/W2149055332","https://openalex.org/W2153690880","https://openalex.org/W2155551886","https://openalex.org/W2157083490","https://openalex.org/W2158174031","https://openalex.org/W2166481560","https://openalex.org/W2167205991","https://openalex.org/W2181187554","https://openalex.org/W2184173176","https://openalex.org/W2254543658","https://openalex.org/W2293924408","https://openalex.org/W2484483581","https://openalex.org/W2996868602","https://openalex.org/W3099219069","https://openalex.org/W3106114372","https://openalex.org/W4245333092","https://openalex.org/W4285719527","https://openalex.org/W6605950757","https://openalex.org/W6772120062"],"related_works":["https://openalex.org/W1030357071","https://openalex.org/W2171888576","https://openalex.org/W2122895920","https://openalex.org/W1977963439","https://openalex.org/W2158853180","https://openalex.org/W2999811406","https://openalex.org/W1494152240","https://openalex.org/W1572401189","https://openalex.org/W1589619473","https://openalex.org/W2136485767"],"abstract_inverted_index":{"Conventional":[0],"charge-based":[1],"memory":[2,22,28,49,62,150],"usage":[3],"in":[4,155],"low-power":[5],"applications":[6],"is":[7,102,118,159],"facing":[8],"major":[9,106],"challenges.":[10],"Some":[11],"of":[12,69,104,115,197],"these":[13,70],"challenges":[14],"are":[15,52,185],"leakage":[16,75],"current":[17],"for":[18,33,39,86,97,108,169,179],"static":[19],"random":[20,26,47],"access":[21,27,48],"(SRAM)":[23],"and":[24,35,55,76,100,140,152,171,181,189,199,204],"dynamic":[25],"(DRAM),":[29],"additional":[30],"refresh":[31],"operation":[32,78],"DRAM,":[34],"high":[36,94,123],"programming":[37],"voltage":[38],"Flash.":[40],"In":[41,135],"this":[42,116],"paper,":[43],"two":[44],"emerging":[45],"resistive":[46],"(ReRAM)":[50],"technologies":[51],"investigated,":[53],"memristor":[54,99,139,180,203],"spin-transfer":[56],"torque":[57],"(STT)-RAM,":[58],"as":[59],"potential":[60,153,194],"universal":[61],"candidates":[63],"to":[64],"replace":[65],"traditional":[66,148],"ones.":[67],"Both":[68],"nonvolatile":[71],"memories":[72],"support":[73],"zero":[74],"low-voltage":[77],"during":[79],"read":[80],"access,":[81],"which":[82],"makes":[83],"them":[84],"ideal":[85],"devices":[87,178],"with":[88,132,146],"long":[89],"sleep":[90],"time.":[91],"To":[92],"date,":[93],"write":[95,124],"energy":[96,125],"both":[98],"STT-RAM":[101,141],"one":[103],"the":[105,110,122,138,147,190],"inhibitors":[107],"adopting":[109],"technologies.":[111],"The":[112,183],"primary":[113],"contribution":[114],"paper":[117,162],"centered":[119],"on":[120],"addressing":[121],"issue":[126],"by":[127],"trading":[128],"off":[129],"retention":[130],"time":[131],"noise":[133],"margin.":[134],"doing":[136],"so,":[137],"power":[142,151,195],"has":[143],"been":[144],"compared":[145],"six-transistor-SRAM-based":[149],"application":[154],"wireless":[156],"sensor":[157],"nodes":[158],"explored.":[160],"This":[161],"uses":[163],"45-nm":[164],"foundry":[165],"process":[166],"technology":[167],"data":[168],"SRAM":[170],"physics-based":[172],"mathematical":[173],"models":[174],"derived":[175],"from":[176],"real":[177],"STT-RAM.":[182],"simulations":[184],"conducted":[186],"using":[187,202],"MATLAB":[188],"results":[191],"show":[192],"a":[193],"savings":[196],"87%":[198],"77%":[200],"when":[201],"STT-RAM,":[205],"respectively,":[206],"at":[207],"1%":[208],"duty":[209],"cycle.":[210]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":6},{"year":2021,"cited_by_count":6},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":12},{"year":2018,"cited_by_count":9},{"year":2017,"cited_by_count":6},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}