{"id":"https://openalex.org/W2280120462","doi":"https://doi.org/10.1109/tvlsi.2015.2430877","title":"High-Performance Deadlock-Free ID Assignment for Advanced Interconnect Protocols","display_name":"High-Performance Deadlock-Free ID Assignment for Advanced Interconnect Protocols","publication_year":2015,"publication_date":"2015-05-25","ids":{"openalex":"https://openalex.org/W2280120462","doi":"https://doi.org/10.1109/tvlsi.2015.2430877","mag":"2280120462"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2015.2430877","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2015.2430877","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5102077112","display_name":"Hsuan-Ming Chou","orcid":null},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Hsuan-Ming Chou","raw_affiliation_strings":["Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I25846049"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5088718949","display_name":"Yi-Chiao Chen","orcid":"https://orcid.org/0000-0002-9477-209X"},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yi-Chiao Chen","raw_affiliation_strings":["Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I25846049"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5029427413","display_name":"Keng-Hao Yang","orcid":null},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Keng-Hao Yang","raw_affiliation_strings":["Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I25846049"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5063016004","display_name":"Jean Tsao","orcid":null},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Jean Tsao","raw_affiliation_strings":["Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I25846049"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5073382186","display_name":"Shih-Chieh Chang","orcid":"https://orcid.org/0000-0003-0717-6466"},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Shih-Chieh Chang","raw_affiliation_strings":["Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I25846049"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110090558","display_name":"Wen-Ben Jone","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Wen-Ben Jone","raw_affiliation_strings":["department of Electrical Engineering and Computing Systems, University of Cincincati, Cincincati, OH, USA"],"affiliations":[{"raw_affiliation_string":"department of Electrical Engineering and Computing Systems, University of Cincincati, Cincincati, OH, USA","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5056256074","display_name":"Tien-Fu Chen","orcid":"https://orcid.org/0000-0001-6925-893X"},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Tien-Fu Chen","raw_affiliation_strings":["Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I25846049"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":7,"corresponding_author_ids":["https://openalex.org/A5102077112"],"corresponding_institution_ids":["https://openalex.org/I25846049"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.13967739,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"24","issue":"3","first_page":"1169","last_page":"1173"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10772","display_name":"Distributed systems and fault tolerance","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7789748907089233},{"id":"https://openalex.org/keywords/database-transaction","display_name":"Database transaction","score":0.6842409372329712},{"id":"https://openalex.org/keywords/deadlock","display_name":"Deadlock","score":0.6371203064918518},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.6367866396903992},{"id":"https://openalex.org/keywords/transaction-processing","display_name":"Transaction processing","score":0.5230154395103455},{"id":"https://openalex.org/keywords/deadlock-prevention-algorithms","display_name":"Deadlock prevention algorithms","score":0.45095953345298767},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.442894846200943},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.4388091564178467},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4320603609085083},{"id":"https://openalex.org/keywords/concurrency-control","display_name":"Concurrency control","score":0.42010441422462463},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.36145323514938354}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7789748907089233},{"id":"https://openalex.org/C75949130","wikidata":"https://www.wikidata.org/wiki/Q848010","display_name":"Database transaction","level":2,"score":0.6842409372329712},{"id":"https://openalex.org/C159023740","wikidata":"https://www.wikidata.org/wiki/Q623276","display_name":"Deadlock","level":2,"score":0.6371203064918518},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.6367866396903992},{"id":"https://openalex.org/C72108876","wikidata":"https://www.wikidata.org/wiki/Q844565","display_name":"Transaction processing","level":3,"score":0.5230154395103455},{"id":"https://openalex.org/C113429609","wikidata":"https://www.wikidata.org/wiki/Q4060699","display_name":"Deadlock prevention algorithms","level":3,"score":0.45095953345298767},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.442894846200943},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.4388091564178467},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4320603609085083},{"id":"https://openalex.org/C84511453","wikidata":"https://www.wikidata.org/wiki/Q2914952","display_name":"Concurrency control","level":3,"score":0.42010441422462463},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.36145323514938354},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2015.2430877","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2015.2430877","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Peace, Justice and strong institutions","score":0.6100000143051147,"id":"https://metadata.un.org/sdg/16"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W1686420892","https://openalex.org/W1980321924","https://openalex.org/W1988975553","https://openalex.org/W3152703111","https://openalex.org/W6637151178"],"related_works":["https://openalex.org/W2050076411","https://openalex.org/W4226119751","https://openalex.org/W1542183432","https://openalex.org/W2360686363","https://openalex.org/W2001478969","https://openalex.org/W1900787600","https://openalex.org/W2340131066","https://openalex.org/W2358822739","https://openalex.org/W4231261802","https://openalex.org/W2361416822"],"abstract_inverted_index":{"In":[0,102],"a":[1,15,50,107],"modern":[2],"system-on-chip":[3],"design,":[4],"hundreds":[5],"of":[6,34,43,128],"cores":[7],"and":[8,40,90,120,148],"intellectual":[9],"properties":[10],"can":[11,97],"be":[12,19,118],"integrated":[13],"into":[14],"single":[16],"chip.":[17],"To":[18,45,80],"suitable":[20],"for":[21],"high-performance":[22],"interconnects,":[23],"designers":[24],"increasingly":[25],"adopt":[26],"advanced":[27,66],"interconnect":[28],"protocols":[29,67],"that":[30,73,112],"support":[31],"novel":[32,48,108],"mechanisms":[33],"parallel":[35],"accessing,":[36],"including":[37],"outstanding":[38],"transactions":[39,89,116],"out-of-order":[41,62],"completion":[42],"transactions.":[44],"implement":[46],"those":[47],"mechanisms,":[49],"master":[51],"tags":[52],"an":[53],"ID":[54,109],"to":[55,58,70,117],"each":[56],"transaction":[57,71,129],"decide":[59],"in-order":[60],"or":[61],"properties.":[63],"However,":[64],"these":[65],"may":[68],"lead":[69],"deadlocks":[72],"do":[74],"not":[75],"occur":[76],"in":[77,91,122,125],"traditional":[78],"protocols.":[79],"prevent":[81],"the":[82,114,126],"deadlock":[83],"problem,":[84],"current":[85],"solutions":[86],"stall":[87],"suspicious":[88],"certain":[92],"cases,":[93],"many":[94],"such":[95],"stalls":[96,130],"incur":[98],"serious":[99],"performance":[100,139],"penalty.":[101],"this":[103],"brief,":[104],"we":[105],"propose":[106],"assignment":[110],"mechanism":[111],"guarantees":[113],"issued":[115,131],"deadlock-free":[119],"results":[121,136],"significant":[123],"reduction":[124],"number":[127],"by":[132],"masters.":[133],"Our":[134],"experimental":[135],"show":[137],"encouraging":[138],"improvements":[140],"compared":[141],"with":[142,145],"previous":[143],"works":[144],"little":[146],"hardware":[147],"power":[149],"overheads.":[150]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}