{"id":"https://openalex.org/W2036678200","doi":"https://doi.org/10.1109/tvlsi.2015.2417595","title":"Hardware Architectural Support for Caching Partitioned Reconfigurations in Reconfigurable Systems","display_name":"Hardware Architectural Support for Caching Partitioned Reconfigurations in Reconfigurable Systems","publication_year":2015,"publication_date":"2015-04-16","ids":{"openalex":"https://openalex.org/W2036678200","doi":"https://doi.org/10.1109/tvlsi.2015.2417595","mag":"2036678200"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2015.2417595","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2015.2417595","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://eprints.ucm.es/id/eprint/31329/1/Hardware....pdf","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5091535324","display_name":"Juan Antonio Clemente","orcid":"https://orcid.org/0000-0002-7855-1051"},"institutions":[{"id":"https://openalex.org/I121748325","display_name":"Universidad Complutense de Madrid","ror":"https://ror.org/02p0gd045","country_code":"ES","type":"education","lineage":["https://openalex.org/I121748325"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Juan Antonio Clemente","raw_affiliation_strings":["Department of Computer Architecture, Universidad Complutense de Madrid, Madrid, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Architecture, Universidad Complutense de Madrid, Madrid, Spain","institution_ids":["https://openalex.org/I121748325"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5035870105","display_name":"Rub\u00e9n Gran Tejero","orcid":"https://orcid.org/0000-0002-4031-5651"},"institutions":[{"id":"https://openalex.org/I255234318","display_name":"Universidad de Zaragoza","ror":"https://ror.org/012a91z28","country_code":"ES","type":"education","lineage":["https://openalex.org/I255234318"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Ruben Gran","raw_affiliation_strings":["Department of Computer Engineering, Universidad de Zaragoza, Zaragoza, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, Universidad de Zaragoza, Zaragoza, Spain","institution_ids":["https://openalex.org/I255234318"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5079865036","display_name":"Abel Chocano","orcid":null},"institutions":[{"id":"https://openalex.org/I121748325","display_name":"Universidad Complutense de Madrid","ror":"https://ror.org/02p0gd045","country_code":"ES","type":"education","lineage":["https://openalex.org/I121748325"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Abel Chocano","raw_affiliation_strings":["Department of Computer Architecture, Universidad Complutense de Madrid, Madrid, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Architecture, Universidad Complutense de Madrid, Madrid, Spain","institution_ids":["https://openalex.org/I121748325"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5060286462","display_name":"Carlos del Prado","orcid":null},"institutions":[{"id":"https://openalex.org/I4210097190","display_name":"Telef\u00f3nica (Spain)","ror":"https://ror.org/012f7tj07","country_code":"ES","type":"company","lineage":["https://openalex.org/I4210097190"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Carlos del Prado","raw_affiliation_strings":["Telef\u00f3nica, Madrid, Spain","[Telefonica, Madrid, Spain]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Telef\u00f3nica, Madrid, Spain","institution_ids":["https://openalex.org/I4210097190"]},{"raw_affiliation_string":"[Telefonica, Madrid, Spain]","institution_ids":["https://openalex.org/I4210097190"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5003490802","display_name":"Javier Resano","orcid":"https://orcid.org/0000-0002-7532-2720"},"institutions":[{"id":"https://openalex.org/I255234318","display_name":"Universidad de Zaragoza","ror":"https://ror.org/012a91z28","country_code":"ES","type":"education","lineage":["https://openalex.org/I255234318"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Javier Resano","raw_affiliation_strings":["Department of Computer Engineering, Universidad de Zaragoza, Zaragoza, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, Universidad de Zaragoza, Zaragoza, Spain","institution_ids":["https://openalex.org/I255234318"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.6589,"has_fulltext":true,"cited_by_count":7,"citation_normalized_percentile":{"value":0.69818653,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":"24","issue":"2","first_page":"530","last_page":"543"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.9113644361495972},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.759768009185791},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.7124877572059631},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.6350539922714233},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6265861988067627},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5833153128623962},{"id":"https://openalex.org/keywords/controller","display_name":"Controller (irrigation)","score":0.5433417558670044},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.5293959975242615},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.4655267596244812},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4628863036632538},{"id":"https://openalex.org/keywords/memory-refresh","display_name":"Memory refresh","score":0.4151836335659027},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.391736775636673},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.3669516444206238},{"id":"https://openalex.org/keywords/computer-memory","display_name":"Computer memory","score":0.24494579434394836},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.13383695483207703}],"concepts":[{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.9113644361495972},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.759768009185791},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.7124877572059631},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.6350539922714233},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6265861988067627},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5833153128623962},{"id":"https://openalex.org/C203479927","wikidata":"https://www.wikidata.org/wiki/Q5165939","display_name":"Controller (irrigation)","level":2,"score":0.5433417558670044},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.5293959975242615},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.4655267596244812},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4628863036632538},{"id":"https://openalex.org/C87907426","wikidata":"https://www.wikidata.org/wiki/Q6815755","display_name":"Memory refresh","level":4,"score":0.4151836335659027},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.391736775636673},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.3669516444206238},{"id":"https://openalex.org/C92855701","wikidata":"https://www.wikidata.org/wiki/Q5830907","display_name":"Computer memory","level":3,"score":0.24494579434394836},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.13383695483207703},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C6557445","wikidata":"https://www.wikidata.org/wiki/Q173113","display_name":"Agronomy","level":1,"score":0.0}],"mesh":[],"locations_count":4,"locations":[{"id":"doi:10.1109/tvlsi.2015.2417595","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2015.2417595","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},{"id":"pmh:oai:dnet:eprintscompl::2c4d851e2ad7cbcfab848e746da2a519","is_oa":true,"landing_page_url":null,"pdf_url":"https://eprints.ucm.es/id/eprint/31329/1/Hardware....pdf","source":{"id":"https://openalex.org/S4306402641","display_name":"LA Referencia (Red Federada de Repositorios Institucionales de Publicaciones Cient\u00edficas)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4383465926","host_organization_name":"LA Referencia","host_organization_lineage":["https://openalex.org/I4383465926"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"acceptedVersion","is_accepted":true,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/article"},{"id":"pmh:oai:www.ucm.es:31329","is_oa":true,"landing_page_url":"http://eprints.ucm.es/31329/1/Hardware....pdf","pdf_url":null,"source":{"id":"https://openalex.org/S4306400298","display_name":"Library Open Repository (Universidad Complutense Madrid)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I121748325","host_organization_name":"Universidad Complutense de Madrid","host_organization_lineage":["https://openalex.org/I121748325"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/article"},{"id":"pmh:oai:zaguan.unizar.es:69448","is_oa":false,"landing_page_url":"http://zaguan.unizar.es/record/69448","pdf_url":null,"source":{"id":"https://openalex.org/S4306401812","display_name":"Zaguan (University of Zaragoza Repository)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I255234318","host_organization_name":"Universidad de Zaragoza","host_organization_lineage":["https://openalex.org/I255234318"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/article"}],"best_oa_location":{"id":"pmh:oai:dnet:eprintscompl::2c4d851e2ad7cbcfab848e746da2a519","is_oa":true,"landing_page_url":null,"pdf_url":"https://eprints.ucm.es/id/eprint/31329/1/Hardware....pdf","source":{"id":"https://openalex.org/S4306402641","display_name":"LA Referencia (Red Federada de Repositorios Institucionales de Publicaciones Cient\u00edficas)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4383465926","host_organization_name":"LA Referencia","host_organization_lineage":["https://openalex.org/I4383465926"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"acceptedVersion","is_accepted":true,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/article"},"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.9100000262260437,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320338080","display_name":"European Social Fund","ror":"https://ror.org/00k4n6c32"}],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2036678200.pdf","grobid_xml":"https://content.openalex.org/works/W2036678200.grobid-xml"},"referenced_works_count":20,"referenced_works":["https://openalex.org/W1754238276","https://openalex.org/W1967981240","https://openalex.org/W1977850862","https://openalex.org/W2000036939","https://openalex.org/W2024122052","https://openalex.org/W2063534452","https://openalex.org/W2064137575","https://openalex.org/W2078159922","https://openalex.org/W2114477097","https://openalex.org/W2117170259","https://openalex.org/W2128373173","https://openalex.org/W2130548217","https://openalex.org/W2135975985","https://openalex.org/W2155484023","https://openalex.org/W2165780643","https://openalex.org/W2169174015","https://openalex.org/W2171385931","https://openalex.org/W3152212851","https://openalex.org/W4243912920","https://openalex.org/W6637903882"],"related_works":["https://openalex.org/W2007744624","https://openalex.org/W2533645807","https://openalex.org/W2760049414","https://openalex.org/W2588527109","https://openalex.org/W2095322762","https://openalex.org/W2010564699","https://openalex.org/W2808635328","https://openalex.org/W2118776233","https://openalex.org/W2019238062","https://openalex.org/W2036678200"],"abstract_inverted_index":{"The":[0],"efficiency":[1],"of":[2,70,83,100,118,175],"the":[3,23,30,38,59,68,71,98,101,131,138,144,161,173,176],"reconfiguration":[4,31,60,123],"process":[5,61],"in":[6,22,55],"modern":[7],"field-programmable":[8],"gate":[9],"arrays":[10],"(FPGAs)":[11],"can":[12,27],"improve":[13,58],"drastically":[14],"if":[15],"an":[16,84],"on-chip":[17,40,72,85,102,134,177],"configuration":[18,73,86,146],"memory":[19,41,74,87],"is":[20,48,75,187],"included":[21],"system,":[24],"because":[25],"it":[26,47,149,192],"reduce":[28],"both":[29],"latency":[32],"and":[33,135,190],"its":[34,184],"energy":[35],"consumption.":[36],"However,":[37],"FPGA":[39],"resources":[42],"are":[43],"very":[44,49,188],"limited.":[45],"Thus,":[46],"important":[50],"to":[51,57,96,108,143],"manage":[52],"them":[53],"effectively":[54],"order":[56,95],"as":[62,64],"much":[63],"possible,":[65],"even":[66],"when":[67],"size":[69],"small.":[76],"This":[77],"paper":[78],"presents":[79],"a":[80,122,165],"hardware":[81],"implementation":[82,185],"controller":[88,105,129,163],"that":[89,112,170,183,191],"efficiently":[90],"manages":[91],"run-time":[92,195],"reconfigurations.":[93],"In":[94],"optimize":[97],"use":[99],"memory,":[103],"this":[104,159],"includes":[106],"support":[107],"deal":[109],"with":[110],"configurations":[111],"have":[113],"been":[114],"divided":[115],"into":[116],"blocks":[117,132,140,153],"customizable":[119],"size.":[120],"When":[121],"must":[124,154],"be":[125,155],"carried":[126],"out,":[127],"our":[128],"provides":[130],"stored":[133,156],"looks":[136],"for":[137],"remaining":[139],"by":[141],"accessing":[142],"off-chip":[145],"memory.":[147],"Moreover,":[148],"dynamically":[150],"decides":[151],"which":[152],"on-chip.":[157],"To":[158],"end,":[160],"designed":[162],"implements":[164],"simple":[166],"but":[167],"efficient":[168],"technique":[169],"allows":[171],"maximizing":[172],"benefits":[174],"memories.":[178],"Experimental":[179],"results":[180],"will":[181],"demonstrate":[182],"cost":[186],"affordable":[189],"introduces":[193],"negligible":[194],"management":[196],"overheads.":[197]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2022,"cited_by_count":2},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}