{"id":"https://openalex.org/W2016046069","doi":"https://doi.org/10.1109/tvlsi.2015.2409297","title":"Source Coding and Preemphasis for Double-Edged Pulsewidth Modulation Serial Communication","display_name":"Source Coding and Preemphasis for Double-Edged Pulsewidth Modulation Serial Communication","publication_year":2015,"publication_date":"2015-03-19","ids":{"openalex":"https://openalex.org/W2016046069","doi":"https://doi.org/10.1109/tvlsi.2015.2409297","mag":"2016046069"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2015.2409297","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2015.2409297","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100392035","display_name":"Wei Wang","orcid":"https://orcid.org/0000-0002-6346-2216"},"institutions":[{"id":"https://openalex.org/I36258959","display_name":"University of California San Diego","ror":"https://ror.org/0168r3w48","country_code":"US","type":"education","lineage":["https://openalex.org/I36258959"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Wei Wang","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of California at San Diego, La Jolla, CA, USA","Department of Electrical and Computer Engineering, University of California at San Diego, La Jolla, CA, USA#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of California at San Diego, La Jolla, CA, USA","institution_ids":["https://openalex.org/I36258959"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of California at San Diego, La Jolla, CA, USA#TAB#","institution_ids":["https://openalex.org/I36258959"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5024558404","display_name":"James F. Buckwalter","orcid":"https://orcid.org/0000-0002-9390-0897"},"institutions":[{"id":"https://openalex.org/I36258959","display_name":"University of California San Diego","ror":"https://ror.org/0168r3w48","country_code":"US","type":"education","lineage":["https://openalex.org/I36258959"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"James F. Buckwalter","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of California at San Diego, La Jolla, CA, USA","Department of Electrical and Computer Engineering, University of California at San Diego, La Jolla, CA, USA#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of California at San Diego, La Jolla, CA, USA","institution_ids":["https://openalex.org/I36258959"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of California at San Diego, La Jolla, CA, USA#TAB#","institution_ids":["https://openalex.org/I36258959"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.06035869,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"24","issue":"2","first_page":"555","last_page":"566"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9936000108718872,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5777259469032288},{"id":"https://openalex.org/keywords/transmitter","display_name":"Transmitter","score":0.5704532861709595},{"id":"https://openalex.org/keywords/transceiver","display_name":"Transceiver","score":0.5586400032043457},{"id":"https://openalex.org/keywords/interleaving","display_name":"Interleaving","score":0.5546490550041199},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5291046500205994},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5226283073425293},{"id":"https://openalex.org/keywords/bit-error-rate","display_name":"Bit error rate","score":0.502723217010498},{"id":"https://openalex.org/keywords/gigabit","display_name":"Gigabit","score":0.4753667712211609},{"id":"https://openalex.org/keywords/bicmos","display_name":"BiCMOS","score":0.44119778275489807},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.32804638147354126},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.3066850006580353},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2892181873321533},{"id":"https://openalex.org/keywords/channel","display_name":"Channel (broadcasting)","score":0.266998291015625},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.1810607612133026},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.14216813445091248}],"concepts":[{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5777259469032288},{"id":"https://openalex.org/C47798520","wikidata":"https://www.wikidata.org/wiki/Q190157","display_name":"Transmitter","level":3,"score":0.5704532861709595},{"id":"https://openalex.org/C7720470","wikidata":"https://www.wikidata.org/wiki/Q954187","display_name":"Transceiver","level":3,"score":0.5586400032043457},{"id":"https://openalex.org/C28034677","wikidata":"https://www.wikidata.org/wiki/Q17092530","display_name":"Interleaving","level":2,"score":0.5546490550041199},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5291046500205994},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5226283073425293},{"id":"https://openalex.org/C56296756","wikidata":"https://www.wikidata.org/wiki/Q840922","display_name":"Bit error rate","level":3,"score":0.502723217010498},{"id":"https://openalex.org/C21922175","wikidata":"https://www.wikidata.org/wiki/Q3105497","display_name":"Gigabit","level":2,"score":0.4753667712211609},{"id":"https://openalex.org/C62427370","wikidata":"https://www.wikidata.org/wiki/Q173416","display_name":"BiCMOS","level":4,"score":0.44119778275489807},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.32804638147354126},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.3066850006580353},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2892181873321533},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.266998291015625},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.1810607612133026},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.14216813445091248}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2015.2409297","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2015.2409297","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.8600000143051147}],"awards":[{"id":"https://openalex.org/G934859203","display_name":null,"funder_award_id":"0901273","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"}],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"},{"id":"https://openalex.org/F4320332180","display_name":"Defense Advanced Research Projects Agency","ror":"https://ror.org/02caytj08"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":43,"referenced_works":["https://openalex.org/W1544623790","https://openalex.org/W1548579702","https://openalex.org/W1970289407","https://openalex.org/W1976772885","https://openalex.org/W1982606279","https://openalex.org/W1988362789","https://openalex.org/W1994355453","https://openalex.org/W2002743180","https://openalex.org/W2006425240","https://openalex.org/W2021633363","https://openalex.org/W2028702143","https://openalex.org/W2031726803","https://openalex.org/W2052133699","https://openalex.org/W2069169282","https://openalex.org/W2080039529","https://openalex.org/W2080728704","https://openalex.org/W2082306786","https://openalex.org/W2082869673","https://openalex.org/W2099000151","https://openalex.org/W2101048469","https://openalex.org/W2106013852","https://openalex.org/W2110286059","https://openalex.org/W2113047903","https://openalex.org/W2120907638","https://openalex.org/W2126647846","https://openalex.org/W2133158895","https://openalex.org/W2136162088","https://openalex.org/W2136837996","https://openalex.org/W2136940543","https://openalex.org/W2137221607","https://openalex.org/W2145047676","https://openalex.org/W2145923236","https://openalex.org/W2150983492","https://openalex.org/W2164893802","https://openalex.org/W2165106386","https://openalex.org/W2168391258","https://openalex.org/W2303012689","https://openalex.org/W2306738904","https://openalex.org/W6645379654","https://openalex.org/W6648592656","https://openalex.org/W6657672093","https://openalex.org/W6663775008","https://openalex.org/W6671555907"],"related_works":["https://openalex.org/W1655266410","https://openalex.org/W1989703526","https://openalex.org/W2169580068","https://openalex.org/W2054088497","https://openalex.org/W2798426149","https://openalex.org/W2010018680","https://openalex.org/W2069396942","https://openalex.org/W2110290642","https://openalex.org/W2132478177","https://openalex.org/W1545944369"],"abstract_inverted_index":{"Double-edged":[0],"pulsewidth":[1],"modulation":[2],"(DPWM)":[3],"is":[4,63,89,98,132],"less":[5],"sensitive":[6],"to":[7,36,70],"frequency-dependent":[8],"losses":[9],"in":[10,56,100],"electrical":[11],"chip-to-chip":[12],"interconnects.":[13],"However,":[14],"the":[15,39,43,51,57,72,128],"DPWM":[16,44,77,96],"scheme":[17,35],"instantaneously":[18],"transmits":[19],"information":[20],"at":[21,109,135],"a":[22,26,68,76,86,101],"different":[23],"rate":[24,119],"than":[25],"synchronous":[27,46],"source.":[28],"This":[29],"paper":[30],"presents":[31],"an":[32],"8-/9-bit":[33,129],"line-coding":[34],"compensate":[37],"for":[38,91],"timing":[40],"skew":[41],"between":[42],"and":[45,59,65,107,120],"clock":[47],"domains":[48],"while":[49],"limiting":[50],"size":[52],"of":[53,75,127],"buffering":[54],"required":[55],"transmitter":[58],"receiver.":[60],"Furthermore,":[61],"preemphasis":[62],"introduced":[64],"analyzed":[66],"as":[67],"means":[69],"improve":[71],"signal":[73],"integrity":[74],"signal.":[78],"A":[79],"multiphase-based,":[80],"time":[81],"interleaving":[82],"receiver":[83],"architecture":[84],"using":[85],"sense":[87],"amplifier":[88],"presented":[90],"high-speed":[92],"data":[93],"recovery.":[94],"The":[95,124],"transceiver":[97],"implemented":[99],"45-nm":[102],"CMOS":[103],"Silicon":[104],"on":[105],"insulator":[106],"operates":[108],"10":[110,113,136],"Gbit/s":[111,137],"with":[112],"<sup":[114],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[115],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">-12</sup>":[116],"bit":[117],"error":[118],"consumes":[121],"96":[122],"mW.":[123],"power":[125],"consumption":[126],"coding":[130],"hardware":[131],"1.5":[133],"mW":[134],"demonstrating":[138],"low-power":[139],"overhead.":[140]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":3}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}